功率器件嵌入PCB技术介绍-电子发烧友网

最近看到功率器件嵌入PCB的应用，了解了一下，感觉很有前景。照这个趋势，将来会以PCB封装各种芯片、被动器件，控制器逐渐器件化，整个供应链缩短，控制器公司转变为PCB级芯片公司，需求量会大量减少。要不去整机厂，要不去搞封装，感觉又一波失业。不过应该对工艺要求很高，到批量还需要时间。有没有这样的工作机会，尽快找一个为未来十年积累一点资本。

一、纬湃科技《PCB嵌入式功率模块技术走势分析和应用前景》

印刷电路板（PCB）天然具有以下优异的电气性能：PCB可以进行多层布线，通过控制线间距及层间距减少EMC的影响，绝缘材料可以满足400~1000V高压绝缘的要求，并且埋入PCB的电子器件可以通过高散热材料和合理的散热层设计达到优秀的散热性能。这些性能优势使得PCB嵌入功率芯片技术用于功率模块封装设计具有极大的性能潜力。

通过技术评估，我们认为相较于传统封装形式，PCB嵌入式功率模块单位半导体的通流能力可以提升约40%，或者同样电流输出使用的半导体用量减少1/3。同样功率输出条件下，功率模块物料成本有望降低20%。

由于新型封装的功率换流回路杂感可降低到1nH以下，使得逆变器的整体开关损耗降低到原有逆变器产品的1/3，从而开关频率的提升所带来的开关损耗的增加相对于传统逆变器降低了2/3。整车上可以通过提高开关频率来提升电驱系统整体的效率，从而基于同样的续航里程减少了电池的用量，最终达到整车降本的目的。同时更高的开关频率使得更小的逆变器体积，以及同样极对数下控制更高速的电机成为可能。

基于目前样品进行的AQG324关键可靠性验证表明，PCB嵌入式封装的设计寿命可达传统封装的数倍。基于这一结果，纬湃科技做了一定的探索，测试PCB材料对功率芯片的高工作结温的耐受，PCB对不同工况下的温度变化的耐受，以及PCB工作在高电压大电流工况下的绝缘性能等。纬湃科技发挥多年来在传统封装设计中积累的经验，攻克多种技术挑战，最终将完成PCB嵌入式功率模块的产业化。

https://mp.weixin.qq.com/s/HZMsUVoGpSz_B4oF_lbWfA

二、2024年5月麦格纳在USA CTI

https://mp.weixin.qq.com/s/hS9qpSWBojdSRGcZKxauNw

三、英飞凌和 Schweizer Electronic合作片

Infineon’s S-Cell 1200 V CoolSiC Gen2p chips

SCHWEIZER 出品的（智能）p² 封装是一种将功率半导体嵌入印制电路板的技术。这种方法不仅仅是一种新封装方法。确切而言，其作用是能根据完全不同的原理来研发电力电子系统。利用智能 p² 封装技术研发的应用可实现高功率、紧凑结构形式和高集成深度。系统供应商的制造链以及系统中的构建和连接技术都明显得以简化。此外，从系统层面也开始有了节省成本的潜力。

热阻更低

由于系统中的电感更小，因此开关损耗更低

静态情况下的传导损耗更低

可实现更高功率密度，因此对硅的需求更小

明显提高产品的坚固性和使用寿命

如下视频中介绍p² 封装信息

schweizer.ag/fileadmin/user_upload/P2_Pack_Full_V3-720p.mp4

文章《Advancing Electric Vehicles with Innovative Chip Embedding and Driver Technology》报道了测试性能。Infineon-Chip_Embedding_for_Silcon_Carbide-Article-v01_00-EN.pdf

Double pulse measurements In figure 4 a recorded turn-off waveform can be seen. The board was operated at room temperature with a turn-off resistance of 10Ω and a DC link voltage of 800V. The switched off current is 114A. The top graph shows the measured drain current id,ls and drain-source voltage vds,ls of the low-side MOSFET. The lower graph depicts the gate-source voltage vgs,ls. The gate voltage shows a very smooth shape, first discharging the input capacitance. Then as the drain-source voltage starts to rise the miller plateau can be seen. The current reduction in this phase is due to the discharging of the high-side MOSFET during the voltage rise of vds,ls. After forward biasing the high-side body diode the current decreases rapidly. Due to the low inductive design (~2nH) of the switching cell the magnitude of voltage overshoot is minimal. Also, ringing is very low, facilitating to reach EMI targets in the drivetrain. With the demonstrator board, measurements of up to 100 V/ns (turn-off) and 28 A/ ns (diode turn-off) are performed showing no inherent limitations from Infineon’s CoolSiC technology.

Short circuit measurements and DESAT detection The designed measurement board is also used to test the short circuit behavior of the 1200 V CoolSiC Gen2p under very low-inductive and fast-switching applications. As the shunt resistor cannot withstand the high pulse energy in a short circuit event, it is removed and replaced with a copper sheet. This copper sheet is soldered to the pads of the shunt resistor so that a Rogowski coil can be used. The 3rd generation EiceDRIVER features very low blanking (ideal for SiC), detection and reaction times for the inbuilt DESAT functionality. Measured waveforms can be seen in figure 5. The top figure shows the current for different desaturation capacitors, while the middle and bottom graphs show the drain-source voltage and gate-source voltage. Following a very fast current-rise of 55 A/ns(Rg,on,ext = 0Ω) the current saturates at around 1200 A. Subsequently, the self-heating effect can be seen leading to a reduced saturation current, before turning off the MOSFET via the SOFTOFF pin. It takes the driver only 456 ns after the turn-on (VEE+1.5V) of the driver stage to detect and react (VCC -1.5 V) to the short circuit event. A minimum short circuit time of 549 ns (according to [5]) is reached, showing the striking performance of the combination of an Infineon EiceDRIVER together with an embedded solution. Despite high peak power, the energy reached with the setup is far below the destruction energy of the chip.