专题74ls54与或非门引脚图及功能表

54/7454四路输入与或非门简要说明54 为与或非门（正逻辑），其中 54/7454 是 2－2－2－2 输入端，54/74H54 是 2－2－3－2 输入端，54/74LS54 是 2－3－3－2 输入端，其主要电特性

02 为四组2 输入端或非门（正逻辑），共有54/7402、54/74S02、54/74LS02 三种线路结构型式，其主要电特性的典型值

74LS系列功能表 74系列全套

GD32E232Kx 引脚介绍注：绿色为容忍5V引脚名称引脚号引脚类型DefaultAlternateAdditionalPF0-OSCIN1I/0PF0I2C0_SDAOSCIN, CLAIN16PF1-OSCOUT2I/0PF1I2C0_SCLOSCOUT,CLAIN17NRST3I/0NRSTVref4PVREFVDDA5PVDDAPA0-WKUP6I/0PA0USART0_CTS,

stm32f407引脚功能表1 主功能就是STM32基本IO口，与外设没有连接的，我们可以直接输出或读入高低电平使用时采用要初始化GPIO结构体参数，并打开端口的时钟2 默认复用功能是与外设连接的IO口，单片机通过控制IO口控制外设。使用时采用要初始化GPIO结构体参数，IO口的工作模式要更具STM32中文参考手册中，IO口复用功能的设置工作模式，设置时，与主功能的唯一区别就是IO口的工作模式的...

SP9741BA9741芯片引脚功能表分享

单 3 输入或非门-74LVC1G27

四路 2 输入或非门-74ALVC02

双 2 输入或非门-74LVC2G02

四路 2 输入或非门-74LV02

四路 2 输入或非门-74LV02A

双 4 输入或非门-74HC4002

单 2 输入或非门-74LVC1G02

四路 2 输入或非门-74LVC02A

本资料有74ls138真值表_74ls138功能表。

74LS90逻辑电路图如图3.6-1所示，它由四个主从JK触发器和一些附加门电路组成，整个电路可分两部分，其中FA触发器构成一位二进制计数器；FD、FC、FB构成异步五进制计数器，在74LS90计数器电路中，设有专用置“0”端R1、R2和置位（置“9”）端S1、S2。

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00 为四组2 输入端与非门（正逻辑），共有54/7400、54/74H00、54/74S00、54/74LS00四种线路结构形式，其主要电特性的典型值如下：

本文档的主要内容详细介绍的是74LS03和54LS03输入与非门的数据手册免费下载。

54/74H01 为集电极开路输出的四组2 输入端与非门（正逻辑），其主要电特性的典型值

Employing complementary MOS (CMOS) transistors toachieve wide power supply operating range, low power consumption,and high noise margin, the CD4070BM/BC andCD4077BM/BC provide basic functions used in the implementationof di

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2 输入单电源转换或非门-74LV1T02

四路 2 输入或非门-74AHC_AHCT02_Q100

四路 2 输入或非门-74AHC_AHCT02

单 2 输入或非门-74LVC1G02_Q100

单 3 输入或非门-74LVC1G27_Q100

2 输入或非门-74HC_HCT1G02_Q100

2 输入或非门-74HC_HCT1G02

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ST6378引脚功能表分享

双 4 输入或非门-74HC_HCT4002

双 2 输入或非门-74HC_HCT2G02

四路 2 输入或非门-74VHC_VHCT02_Q100

双 2 输入或非门-74LVC2G02_Q100

2 输入或非门-74AHC_AHCT1G02_Q100

四路 2 输入或非门-74HC_HCT02_Q100

低功耗双路 2 输入或非门-74AUP2G02

四路 2 输入或非门-74LVC02A_Q100

四路 2 输入或非门-74VHC_VHCT02

低功耗 2 输入或非门-74AUP1G02_Q100

双 4 输入或非门-74HC4002_Q100

3.3 V 四路 2 输入或非门-74LVT02

三路 3 输入或非门-74HC_HCT27_Q100

双 2 输入或非门-74HC_HCT2G02_Q100

低功耗 2 输入或非门-74AXP1G02

四路 2 输入或非门-74HC_HCT02

2 输入或非门-74AHC_AHCT1G02

低功耗 2 输入或非门-74AUP1G02

AiP74LVC2G02规格书下载

三路 3 输入或非门-74HC_HCT27

7402 TTL 2输入端四或非门:

54LS85/DM54LS85/DM74LS854-Bit Magnitude ComparatorsGeneral DescriptionThese 4-bit magnitude comparators perform comparison ofstraight binary or BCD codes. Three fully-decoded decisionsabout two, 4-bit words (A, B) are m

The CD4001BC and CD4011BC quad gates are monolithiccomplementary MOS (CMOS) integrated circuits constructedwith N- and P-channel enhancement mode transistors.They have equal source and sink currentcapabilities and confor

These NOR and NAND gates are monolithic complementaryMOS (CMOS) integrated circuits. The N- and P-channelenhancement mode transistors provide a symmetrical circuitwith output swings essentially equal to the supply voltage.

本帖最后由 gk320830 于 2015-3-9 15:46 编辑

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SN54LS594,

SN54LS292,

These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control function implementation allows for maximum flexibility in timing. These devices allow data transmission from the A bus

This device contains two independent gates each of whichperforms the logic AND function.Y Alternate Military/Aerospace device (54LS21) is avail-able. Contact a National Semiconductor Sales Office/Distributor for specificati

一 、CTYPE.H1、extern bit isalpha (unsigned char); 检查参数字符是否为英文字符，是则返回1，否则返回02、extern bit isalnum (unsigned char); 检查参数字符是否为字母或者数字字符，是则返回1，否则返回03、extern bit iscntrl (unsigned char);检查参数值是否在0x00~0x7F之间或者等于0x7F，是则返回1，否则返回04、extern bit isdigit (unsigned char);检查参数值是否为数字字符，是则返回1，否则返回05、extern bit isgraph (unsigned char);检查参数是否为可打印字符（0x21~0x7E），是则返回1，否则返回06、extern bit isprint (unsigned char);检查参数是否为可打印字符，包括空格符，其余与isgraph相同7、extern bit ispunct (unsigned char);检查参数是否为标点、空格或者格式字符，是则返回1，否则返回08、extern bit islower (unsigned char);检查参数是否为小写字母，是则返回1，否则返回09、extern bit isupper (unsigned char);检查参数是否为大写字母，是则返回1，否则返回010、extern bit isspace (unsigned char);检查参数是否为下列之一：空格、制表符、回车、换行、垂直制表符和送纸符号，是则返回1，否则返回011、extern bit isxdigit (unsigned char);检查参数是否为16进制数字字符，是则返回1，否则返回012、extern unsigned char tolower (unsigned char);将大写字符转换成小写形式，如果字符不在（A~Z）之间，则直接返回该字符13、extern unsigned char toupper (unsigned char);将小写字符转换成大写形式，如果字符不在（a~z）之间，则直接返回该字符14、extern unsigned char toint (unsigned char);将ASCII字符0~9，A~F（不分大小写）转换成16进制的数字，返回转换后的16进制数字 二、STDIO.H #ifndef EOF #define EOF -1#endif #ifndef NULL #define NULL ((void *) 0)#endif #ifndef _SIZE_T #define _SIZE_T typedef unsigned int size_t;#endif 1、extern char _getkey (void);从单片机串口读入一个字符，然后等待字符输入2、extern char getchar (void);该函数使用_getkey()函数从串口读入字符，并将读入的字符马上给putchar()函数输出3、extern char ungetchar (char);将输入的字符回送输入缓冲区，成功返回char，否则返回EOF4、extern char putchar (char);通过单片机的串口输出字符，与_getkey()函数一样5、extern int printf(constchar *, ...);以一定的格式通过单片机串行口输出数值和字符串，返回值为实际输出的字符数6、extern int sprintf(char *,const char *, ...);通过一个指针S将数据送人可寻址的内存缓冲区，并以ASCII码的形式存储7、extern int vprintf(constchar *, char *);8、extern int vsprintf (char *, const char *, char *); 9、extern char *gets (char *, int n); 10、extern int scanf (const char *, ...); 11、extern int sscanf (char *, const char *, ...); 12、extern int puts (const char *); 三、string.h 1、extern char *strcat (char *s1, char *s2); 2、extern char *strncat (char *s1, char *s2, int n); 3、extern char strcmp (char *s1, char *s2);4、extern char strncmp (char *s1, char *s2, int n); 5、extern char *strcpy (char *s1, char *s2);6、extern char *strncpy (char *s1, char *s2, int n); 7、extern int strlen (char *); 8、extern char *strchr (const char *s, char c);9、extern int strpos (const char *s, char c);10、extern char *strrchr (const char *s, char c);11、extern int strrpos (const char *s, char c); 12、extern int strspn (char *s, char *set);13、extern int strcspn (char *s, char *set);14、extern char *strpbrk (char *s, char *set);15、extern char *strrpbrk (char *s, char *set);16、extern char *strstr(char *s,char *sub);17、extern char *strtok(char*str, const char *set); 18、extern char memcmp (void *s1, void *s2, int n);19、extern void *memcpy (void *s1, void *s2, int n);20、extern void *memchr (void *s, char val, int n);21、extern void *memccpy (void *s1, void *s2, char val, int n);22、extern void *memmove (void *s1, void *s2, int n); 23、extern void *memset(void *s,char val, int n); 四、stdlib.h 1、extern int abs(intval);2、extern longlabs(long val); 3、extern float atof (char *s1);将字符串转换成浮点数4、extern longatol (char *s1);将字符串转换成长整型5、extern intatoi (char *s1);将字符串转换成整型6、extern intrand ();取一个0~32767之间的随机数7、extern voidsrand (int);根据种子seed的值取随机数8、extern floatstrtod(char *, char **);9、extern longstrtol(char *, char **, unsignedchar);将字符串转换成长整数10、extern unsigned long strtoul (char *, char **, unsigned char);将字符串转换成无符号长整数#define _MALLOC_MEM_xdata 11、extern void init_mempool(void _MALLOC_MEM_ *p, unsigned int size);初始化内存池12、extern void _MALLOC_MEM_ *malloc (unsigned int size);申请一块大小为size的内存13、extern void free(void _MALLOC_MEM_ *p);释放一块被申请的内存14、extern void _MALLOC_MEM_ *realloc (void _MALLOC_MEM_ *p, unsignedint size);重新申请一块大小为size的内存15、extern void _MALLOC_MEM_ *calloc (unsigned int size, unsigned int len);申请有size个元素的，每个元素的大小为len的数组 五、math.h 1、extern charcabs(char val);计算并返回val的绝对值，为char型2、extern int abs(intval);计算并返回val的绝对值，为int型3、extern longlabs(long val);计算并返回val的绝对值，为long型4、extern float fabs(floatval);计算并返回val的绝对值，为float型5、extern float sqrt(floatval);返回x的正平方根6、extern float exp(floatval);计算e为底x的幂并返回计算结果7、extern float log(floatval);返回自然对数8、extern float log10 (float val);返回以10为底的对数9、extern float sin(floatval);10、extern float cos(floatval);11、extern float tan(floatval);以上3个函数返回相应的三角函数值，所有的变量范围在-π/2 ~ +π/2之间，否则会返回错误12、extern float asin(floatval);13、extern float acos(floatval);14、extern float atan(floatval);返回相应的反三角函数值，值域为-π/2 ~ +π/215、extern float sinh(floatval);16、extern float cosh(floatval);17、extern float tanh(float val);返回x的相应的双曲函数值 18、extern float atan2 (float y, float x);返回x/y的反正切值，值域为-π ~ +π19、extern float ceil(floatval);返回一个不小于val的最小整数（作为浮点数）20、extern float floor (float val);返回一个不大于val最大整数（作为浮点型）21、extern float modf(float val,float *n);将浮点数val分为整数和小数两部分，两者的符号与val相同，整数部分放入*n，小数部分作为返回值22、extern float fmod(float x,float y);返回x/y的余数23、extern float pow(float x,float y);返回x的y次方 六、absacc.h 以下4个宏定义，对单片机的进行绝对地址访问，可以作为字节寻址，CBYTE寻址code区，DBYTE寻址data区，PBYTE寻址分页xdata区，XBYTE寻址xdata区 1、#define CBYTE ((unsigned char volatile code*) 0)2、#define DBYTE ((unsigned char volatile data*) 0)3、#define PBYTE ((unsigned char volatile pdata *) 0)4、#define XBYTE ((unsigned char volatile xdata *) 0) 以上4个宏定义与上面4个功能类似，只是数据类型是unsignedint型5、#define CWORD ((unsigned int volatile code*) 0)6、#define DWORD ((unsigned int volatile data*) 0)7、#define PWORD ((unsigned int volatile pdata *) 0)8、#define XWORD ((unsigned int volatile xdata *) 0) 七、intrins.h 1、extern void_nop_(void);空操作指令，需要一个指令周期2、extern bit_testbit_(bit);该函数对字节中的一个比特进行测试，如果该比特为1则返回1，并置该位为0，否则返回03、extern unsigned char _cror_(unsigned char, unsigned char);4、extern unsigned int _iror_ (unsigned int,unsigned char);5、extern unsigned long _lror_(unsigned long, unsigned char);将第一个参数循环右移n位，3个函数的参数和返回值类型不同6、extern unsigned char _crol_(unsigned char, unsigned char);7、extern unsigned int _irol_ (unsigned int,unsigned char);8、extern unsigned long _lrol_(unsigned long, unsigned char);将第一个参数循环左移n位，3个函数的不同在于参数和返回值的类型9、extern unsigned char _chkfloat_(float);10、extern void_push_ (unsigned char _sfr);11、extern void_pop_(unsigned char _sfr); 八、setjmp.htypedef char jmp_buf[_JBLEN]; 1、extern volatile intsetjmp(jmp_buf); 2、extern volatile void longjmp (jmp_buf, int);

SN54LS422,

SN54LS597,

SN54LS673,

74ls详细资料

介绍  74148优先编码器为16脚的集成芯片，是一复个八线-三线优先级编码器。除电源脚 VCC(16)和GND(8)外，其余输入、输出脚的作用和脚号如图中所标。制其中 I 0— I 7为输入信号， A2,A1,A0为三位二进制编码输出信号， EI是使能输入端， EO使能输出端， G S为片优先编码输出端。  在优先编码器电路中，允许同时输入两个以上编码信号。不过在设计优先编码器时，已经将所有...

These octal buffers and line drivers are designed to have the performance of the popular SN54LS240/SN74LS240 series and, at the same time, offer a pinout having the inputs and outputs on opposite sides of the package. This arrangement g

SN54LS592,

SN54LS595,

54LS32/DM54LS32/DM74LS32Quad 2-Input OR GatesGeneral DescriptionThis device contains four independent gates each of whichperforms the logic OR function.FeaturesY Alternate Military/Aerospace device (54LS32) is avail

54LS168 Synchronous Bi-DirectionalBCD Decade CounterGeneral DescriptionThe 54LS168 is a fully synchronous 4-state up/down counterfeaturing a preset capability for programmable operation,carry lookahead for easy cascadin

54LS368A/DM54LS368A/DM74LS368AHex TRI-STATEÉ Inverting BuffersGeneral DescriptionThis device contains six independent gates each of whichperforms an inverting buffer function. The outputs have theTRI-STATE featur

54LS379/DM74LS379Quad Parallel Register with EnableGeneral DescriptionThe LS379 is a 4-bit register with buffered common Enable.This device is similar to the LS175 but features the commonEnable rather than common Master

54LS38/DM54LS38/DM74LS38Quad 2-Input NAND Bufferswith Open-Collector OutputsGeneral DescriptionThis device contains four independent gates, each of whichperforms the logic NAND function. The open-collector outputsre

54LS49 BCD to 7-Segment DecoderGeneral DescriptionThe 54LS49 translates four lines of BCD (8421) input datainto the 7-segment numeral code as shown in the FunctionTable. It has open-collector outputs and is logically the 14

54LS125A/DM54LS125A/DM74LS125AQuad TRI-STATEÉ BuffersGeneral DescriptionThis device contains four independent gates each of whichperforms a non-inverting buffer function. The outputs havethe TRI-STATE feature. Wh

54LS155/DM54LS155/DM74LS155,54LS156/DM54LS156/DM74LS156Dual 2-Line to 4-Line Decoders/DemultiplexersGeneral DescriptionThese TTL circuits feature dual 1-line-to-4-line demultiplexerswith individual strobes and common bi

54LS253/DM54LS253/DM74LS253TRI-STATEÉ Data Selectors/MultiplexersGeneral DescriptionEach of these Schottky-clamped data selectors/multiplexerscontains inverters and drivers to supply fully complementary,on-chip,

54LS257A/DM54LS257B/DM74LS257B,54LS258A/DM54LS258B/DM74LS258BTRI-STATEÉ Quad 2-Data Selectors/MultiplexersGeneral DescriptionThese Schottky-clamped high-performance multiplexersfeature TRI-STATE outputs that can

54LS257A/DM54LS257B/DM74LS257B,54LS258A/DM54LS258B/DM74LS258BTRI-STATEÉ Quad 2-Data Selectors/MultiplexersGeneral DescriptionThese Schottky-clamped high-performance multiplexersfeature TRI-STATE outputs that can

54LS113Dual JK Edge-Triggered Flip-FlopGeneral DescriptionThe 54LS113 offers individual J, K, Set and Clock inputs.When the clock goes HIGH the inputs are enabled and datamay be entered. The logic level of the J and K i

74LS114/54

54LS157/DM54LS157/DM74LS157,54LS158/DM54LS158/DM74LS158Quad 2-Line to 1-Line Data Selectors/MultiplexersGeneral DescriptionThese data selectors/multiplexers contain inverters anddrivers to supply full on-chip data selec

54LS245/DM54LS245/DM74LS245TRI-STATEÉ Octal Bus TransceiverGeneral DescriptionThese octal bus transceivers are designed for asynchronoustwo-way communication between data buses. Thecontrol function implementation

74LS279/54

54LS670/DM54LS670/DM74LS670TRI-STATEÉ 4-by-4 Register FilesGeneral DescriptionThese register files are organized as 4 words of 4 bits each,and separate on-chip decoding is provided for addressingthe four word loc

54LS283/DM54LS283/DM74LS2834-Bit Binary Adders with Fast CarryGeneral DescriptionThese full adders perform the addition of two 4-bit binarynumbers. The sum (R) outputs are provided for each bit andthe resultant carry (C

DM54LS86/DM74LS86Quad 2-Input Exclusive-OR GatesGeneral DescriptionThis device contains four independent gates each of whichperforms the logic exclusive-OR function.

54LS11/DM54LS11/DM74LS11 Triple 3-Input AND GatesGeneral DescriptionThis device contains three independent gates each of whichperforms the logic AND function.FeaturesY Alternate military/aerospace device (54LS11) is ava

54LS42/DM54LS42/DM74LS42 BCD/Decimal DecodersGeneral DescriptionThese BCD-to-decimal decoders consist of eight invertersand ten, four-input NAND gates. The inverters are connectedin pairs to make BCD input data available fo

54LS112/DM54LS112A/DM74LS112ADual Negative-Edge-Triggered Master-SlaveJ-K Flip-Flops with Preset, Clear,and Complementary OutputsGeneral DescriptionThis device contains two independent negative-edge-triggeredJ-K fli

54LS138/DM54LS138/DM74LS138,54LS139/DM54LS139/DM74LS139Decoders/DemultiplexersGeneral DescriptionThese Schottky-clamped circuits are designed to be used inhigh-performance memory-decoding or data-routing applications,

54LS138/DM54LS138/DM74LS138,54LS139/DM54LS139/DM74LS139Decoders/DemultiplexersGeneral DescriptionThese Schottky-clamped circuits are designed to be used inhigh-performance memory-decoding or data-routing applications,

54LS195A/DM74LS195A4-Bit Parallel Access Shift RegisterGeneral DescriptionThis 4-bit register features parallel inputs, parallel outputs,J-K serial inputs, shift/load control input, and a direct overridingclear. All inp