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The SMJ320C80 is a single-chip, MIMD parallel processor capable of performing over two billion operations per second. It consists of a 32-bit RISC master processor with a 100-MFLOPS (million floating-point operations per second) IEEE floating-point unit, four 32-bit parallel processing digital signal processors (DSPs), a transfer controller with up to 400-MBps off-chip transfer rate, and a video controller. All the processors are coupled tightly through an on-chip crossbar that provides shared access to on-chip RAM. This performance and programmability make the C80 ideally suited for video, imaging, and high-speed telecommunications applications.
IEEE标准1149.1 ?? 1990，IEEE标准测试访问端口和边界扫描架构
| Cycle Time (ns) |
| Data / Program Memory Space (Words) |
| DMA (Ch) |
| Frequency (MHz) |
| MIPS |
| MOPS |
| Operating Temperature Range (C) |
| Package Group |
| Pin/Package |
| Rating |
| SMJ320C80 | SM320C80 |
|---|---|
| 20 | 20 |
| 2.4G | 2.4G |
| 1 | 1 |
| 50 | 50 |
| 60 | 60 |
| 120 | 120 |
| -55 to 125 | -55 to 125 |
| CPGA |
CFP CPGA |
| 305CPGA |
305CPGA 320CFP |
| Military | Military |
| 无样片 | 无样片 |
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