0
  • 聊天消息
  • 系统消息
  • 评论与回复
登录后你可以
  • 下载海量资料
  • 学习在线课程
  • 观看技术视频
  • 写文章/发帖/加入社区
创作中心

完善资料让更多小伙伴认识你,还能领取20积分哦,立即完善>

3天内不再提示

Xilinx FPGA里面的AXI DMA IP核的简单用法

C29F_xilinx_inc 来源:赛灵思 作者:赛灵思 2022-02-16 16:21 次阅读

FPGA里面,AXI DMA这个IP核的主要作用,就是在Verilog语言和C语言之间传输大批量的数据,使用的通信协议为AXI4-Stream。

Xilinx很多IP核都是基于AXI4-Stream协议的,例如浮点数Floating-point IP核,以及以太网Tri Mode Ethernet MAC IP核。要想将Verilog层面的数据搬运到C语言里面处理,就要使用DMA IP核。

本文以浮点数Floating-point IP核将定点数转换为浮点数为例,详细讲解AXI DMA IP核的使用方法。

浮点数IP核的输入输出数据都是32位,协议均为AXI4-Stream。C语言程序首先将要转换的定点数数据通过DMA发送给浮点数IP核,浮点数IP核转换完成后再通过DMA将单精度浮点数结果发回C语言程序,再通过printf打印出来。

定点数的数据类型为int,小数点定在第四位上,即:XXXXXXX.X。整数部分占28位,小数部分占4位。

转换后浮点数的数据类型为float,可以用printf的%f直接打印出来。

工程下载地址:https://pan.baidu.com/s/1SXppHMdhroFT8vGCIysYTQ(提取码:u7wf)

MicroBlaze C语言工程的建法不再赘述,请参阅:https://blog.csdn.net/ZLK1214/article/details/111824576

pYYBAGIMpo2AJqjNAAH_MWNrJUU622.png

首先添加Floating-point IP核,作为DMA的外设端:(主存端为BRAM)

poYBAGIMpo-ANZDbAAA_l0ntfqk097.png

poYBAGIMppCAJxSNAAEGvn8Va34201.png

pYYBAGIMppKAStvHAAEMJT25qmg379.png

poYBAGIMppSAJJnmAAD2VQEXRHw583.png

这里要注意一下,一定要勾选上TLAST,否则DMA接收端会出现DMA Internal Error的错误:

pYYBAGIMppaAVBY2AAFE0VbVX3o575.png

下面是Xilinx DMA手册里面对DMA Internal Error错误的描述:

poYBAGIMppiAHRX6AACbAx3Wn-M539.png

添加AXI DMA IP核:

pYYBAGIMppqARPshAABNz_Q8C2c867.png

IP核添加好了,但还没有连线:

pYYBAGIMppyAV16VAACq-RthNiM037.png

点击Run Connection Automation,自动连接DMA的S_AXI_LITE接口

pYYBAGIMpp6AMfbJAAE2FppS-0I773.png

poYBAGIMpqKAWFqEAAKoYpB4afY616.png

pYYBAGIMpqSALYymAAEFOXj7KkI879.png

pYYBAGIMpqaAPHUkAAFJHM4rMQI008.png

poYBAGIMpqmAUl7LAAEg29w2F28228.png

自动连接浮点数IP核的时钟引脚:

pYYBAGIMpquAEl5bAAFqfrxqB3Q110.png

poYBAGIMpq-ASKUlAAQhpFjGMvY547.png

poYBAGIMprGAOAtYAAFr6mSyUyY366.png

pYYBAGIMprOAElDjAAFLHFr0bfQ712.png

pYYBAGIMprWAKbr4AAKKtr6QNo8705.png

添加BRAM控制器

poYBAGIMpraAWb5LAAAQUOLl1YU793.png

pYYBAGIMpriAEAvhAAG3KfwYg_8873.png

最终的连线结果:

pYYBAGIMprqAfAw4AAK-1KrBJC4019.png

修改新建的BRAM的容量为64KB:

pYYBAGIMpryARkB4AAFxBvZe0Bg340.png

pYYBAGIMpr-AbUYfAAGA3kbuYQ8313.png

最终的地址分配方式:

poYBAGIMpsGAOpbRAAF_bEy5vaE460.png

保存Block Design,然后生成Bitstream:

pYYBAGIMpsOATBaGAAEszSUAiCM178.png

Bitstream生成后,导出xsa文件:

poYBAGIMpsSADsPbAAD1JA0uxRY519.png

Vitis Platform工程重新导入xsa文件:

poYBAGIMpsaARsBwAACII8fJ-zA463.png

poYBAGIMpsmAVEo0AAT3WAEPq1E727.png

修改C程序(helloworld.c)的代码:

(这里面XPAR_BRAM_2_BASEADDR最好改成0xc0000000,因为生成的xparameters.h配置文件里面BRAM号可能有变化)
/******************************************************************************
*
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/

/*
* helloworld.c: simple test application
*
* This application configures UART 16550 to baud rate 9600.
* PS7 UART (Zynq) is not initialized by this application, since
* bootrom/bsp configures it to baud rate 115200
*
* ------------------------------------------------
* | UART TYPE BAUD RATE |
* ------------------------------------------------
* uartns550 9600
* uartlite Configurable only in HW design
* ps7_uart 115200 (configured by bootrom/bsp)
*/

#include
#include
#include "platform.h"

// DMA无法通过AXI Interconnect访问Microblaze本身的BRAM内存
// 只能访问挂接在AXI Interconnect上的内存
#define _countof(arr) (sizeof(arr) / sizeof(*(arr)))
typedef struct
{
int numbers_in[40];
float numbers_out[40];
} BRAM2_Data;

static BRAM2_Data *bram2_data = (BRAM2_Data *)XPAR_BRAM_2_BASEADDR;
static XAxiDma xaxidma;

int main(void)
{
int i, ret = 0;
XAxiDma_Config *xaxidma_cfg;

init_platform();

printf("Hello World\n");
printf("Successfully ran Hello World application\n");

// 初始化DMA
xaxidma_cfg = XAxiDma_LookupConfig(XPAR_AXIDMA_0_DEVICE_ID);
XAxiDma_CfgInitialize(&xaxidma, xaxidma_cfg);
ret = XAxiDma_Selftest(&xaxidma);
if (ret != XST_SUCCESS)
{
printf("XAxiDma_Selftest() failed! ret=%d\n", ret);
goto err;
}

// 初始化DMA的输入数据
printf("numbers_in=%p, numbers_out=%p\n", bram2_data->numbers_in, bram2_data->numbers_out);
for (i = 0; i numbers_in); i++)
{
bram2_data->numbers_in[i] = 314 * (i + 1);
if (i & 1)
bram2_data->numbers_in[i] = -bram2_data->numbers_in[i];
}

// DMA开始发送数据 (Length参数的单位为字节)
ret = XAxiDma_SimpleTransfer(&xaxidma, (uintptr_t)bram2_data->numbers_in, sizeof(bram2_data->numbers_in), XAXIDMA_DMA_TO_DEVICE);
if (ret != XST_SUCCESS)
{
printf("XAxiDma_SimpleTransfer(XAXIDMA_DMA_TO_DEVICE) failed! ret=%d\n", ret);
goto err;
}

// DMA开始接收数据
ret = XAxiDma_SimpleTransfer(&xaxidma, (uintptr_t)bram2_data->numbers_out, sizeof(bram2_data->numbers_out), XAXIDMA_DEVICE_TO_DMA);
if (ret != XST_SUCCESS)
{
printf("XAxiDma_SimpleTransfer(XAXIDMA_DEVICE_TO_DMA) failed! ret=%d\n", ret);
goto err;
}

// 等待DMA发送完毕
i = 0;
while (XAxiDma_Busy(&xaxidma, XAXIDMA_DMA_TO_DEVICE))
{
i++;
if (i == 200000)
{
// 必须确保DMA访问的内存是直接挂接在AXI Interconnect上的
// 否则这里会报DMA Decode Error的错误 (the address request points to an invalid address)
printf("DMA Tx timeout! DMASR=0x%08lx\n", XAxiDma_ReadReg(xaxidma.RegBase + XAXIDMA_TX_OFFSET, XAXIDMA_SR_OFFSET));
goto err;
}
}
printf("DMA Tx complete!\n");

// 等待DMA接收完毕
i = 0;
while (XAxiDma_Busy(&xaxidma, XAXIDMA_DEVICE_TO_DMA))
{
i++;
if (i == 200000)
{
// floating-point IP核的配置里面一定要把A通道的tlast复选框勾选上, 使输入端和输出端都有tlast信号
// 否则s_axis_s2mm_tlast一直为0, DMA以为数据还没接收完, 就会报DMA Internal Error的错误
// (the incoming packet is bigger than what is specified in the DMA length register)
printf("DMA Rx timeout! DMASR=0x%08lx\n", XAxiDma_ReadReg(xaxidma.RegBase + XAXIDMA_RX_OFFSET, XAXIDMA_SR_OFFSET));
goto err;
}
}
printf("DMA Rx complete!\n");

err:
for (i = 0; i numbers_out); i++)
printf("numbers_out[%d]=%f\n", i, bram2_data->numbers_out[i]);

cleanup_platform();
return 0;
}

C程序的运行结果:

pYYBAGIMpsuAAHqIAAOtyw3zrA4278.png

Hello World
Successfully ran Hello World application
numbers_in=0xc0000000, numbers_out=0xc00000a0
DMA Tx complete!
DMA Rx complete!
numbers_out[0]=19.625000
numbers_out[1]=-39.250000
numbers_out[2]=58.875000
numbers_out[3]=-78.500000
numbers_out[4]=98.125000
numbers_out[5]=-117.750000
numbers_out[6]=137.375000
numbers_out[7]=-157.000000
numbers_out[8]=176.625000
numbers_out[9]=-196.250000
numbers_out[10]=215.875000
numbers_out[11]=-235.500000
numbers_out[12]=255.125000
numbers_out[13]=-274.750000
numbers_out[14]=294.375000
numbers_out[15]=-314.000000
numbers_out[16]=333.625000
numbers_out[17]=-353.250000
numbers_out[18]=372.875000
numbers_out[19]=-392.500000
numbers_out[20]=412.125000
numbers_out[21]=-431.750000
numbers_out[22]=451.375000
numbers_out[23]=-471.000000
numbers_out[24]=490.625000
numbers_out[25]=-510.250000
numbers_out[26]=529.875000
numbers_out[27]=-549.500000
numbers_out[28]=569.125000
numbers_out[29]=-588.750000
numbers_out[30]=608.375000
numbers_out[31]=-628.000000
numbers_out[32]=647.625000
numbers_out[33]=-667.250000
numbers_out[34]=686.875000
numbers_out[35]=-706.500000
numbers_out[36]=726.125000
numbers_out[37]=-745.750000
numbers_out[38]=765.375000
numbers_out[39]=-785.000000

poYBAGIMps6AYy8nAAS7yU8SJ_8640.png

接下来讲一下我们刚才禁用掉的Scatter Gather接口的用法。取消禁用后,之前的C代码就不能运行了。
之前没有启用Scatter Gather的时候,我们一次只能提交一个DMA请求,等这个DMA请求的数据传输完毕后,我们才能提交下一个DMA传输请求。
有了Scatter Gather接口,我们就可以一次性提交很多很多DMA请求,然后CPU去干其他的事情。这可以大大提高传输效率。
除此以外,Scatter Gather还可以将多个位于不同内存地址的缓冲区合并成一个AXI4-Stream数据包传输。

下面的示例演示了如何利用Scatter Gather功能批量收发3组数据包。
启用了Scatter Gather后,DMA里面多出了一个M_AXI_SG接口,点击Run Connection Automation,连接到AXI Interconnect上:

pYYBAGIMptCAMQ6zAAKe7D5xcpo553.png

pYYBAGIMptKAF2XMAAZpvcPD86o959.png

Vivado工程Generate Bitstream,然后导出xsa文件。回到Vitis后,必须把Platform工程删了重建,不然XPAR_AXI_DMA_0_INCLUDE_SG的值得不到更新。

poYBAGIMptSAe0AnAADlJnJWhCw515.png

pYYBAGIMptaAS3wVAAbTkOJjG3o749.png

pYYBAGIMptiAXaiaAAg2skXUvyM504.png

原有的C程序不再可用,修改一下程序代码
/******************************************************************************
*
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/

/*
* helloworld.c: simple test application
*
* This application configures UART 16550 to baud rate 9600.
* PS7 UART (Zynq) is not initialized by this application, since
* bootrom/bsp configures it to baud rate 115200
*
* ------------------------------------------------
* | UART TYPE BAUD RATE |
* ------------------------------------------------
* uartns550 9600
* uartlite Configurable only in HW design
* ps7_uart 115200 (configured by bootrom/bsp)
*/

#include
#include
#include "platform.h"

/* Xilinx的官方例程:C:\Xilinx\Vitis\2020.1\data\embeddedsw\XilinxProcessorIPLib\drivers\axidma_v9_11\examples\xaxidma_example_sg_poll.c */

// DMA无法通过AXI Interconnect访问Microblaze本身的BRAM内存
// 只能访问挂接在AXI Interconnect上的内存
#define _countof(arr) (sizeof(arr) / sizeof(*(arr)))
typedef struct
{
int numbers_in[40];
float numbers_out[40];
} BRAM2_Data;

typedef struct
{
uint8_t txbuf[640];
uint8_t rxbuf[640];
} BRAM2_BdRingBuffer;

static BRAM2_Data *bram2_data = (BRAM2_Data *)0xc0000000;
static BRAM2_BdRingBuffer *bram2_bdringbuf = (BRAM2_BdRingBuffer *)0xc0008000;
static XAxiDma xaxidma;

int main(void)
{
int i, n, ret = 0;
XAxiDma_Bd *bd, *p;
XAxiDma_BdRing *txring, *rxring;
XAxiDma_Config *cfg;

init_platform();

printf("Hello World\n");
printf("Successfully ran Hello World application\n");

// 初始化DMA
cfg = XAxiDma_LookupConfig(XPAR_AXIDMA_0_DEVICE_ID);
XAxiDma_CfgInitialize(&xaxidma, cfg);
ret = XAxiDma_Selftest(&xaxidma);
if (ret != XST_SUCCESS)
{
printf("XAxiDma_Selftest() failed! ret=%d\n", ret);
goto err;
}

if (!XAxiDma_HasSg(&xaxidma))
{
printf("XPAR_AXI_DMA_0_INCLUDE_SG=%d\n", XPAR_AXI_DMA_0_INCLUDE_SG);
printf("Please recreate and build Vitis platform project!\n");
goto err;
}

// 初始化DMA的输入数据
printf("[0] numbers_in=%p, numbers_out=%p\n", bram2_data[0].numbers_in, bram2_data[0].numbers_out);
printf("[1] numbers_in=%p, numbers_out=%p\n", bram2_data[1].numbers_in, bram2_data[1].numbers_out);
printf("[2] numbers_in=%p, numbers_out=%p\n", bram2_data[2].numbers_in, bram2_data[2].numbers_out);
for (i = 0; i {
bram2_data[0].numbers_in[i] = 314 * (i + 1);
bram2_data[1].numbers_in[i] = -141 * (i + 1);
bram2_data[2].numbers_in[i] = -2718 * (i + 1);
if (i & 1)
{
bram2_data[0].numbers_in[i] = -bram2_data[0].numbers_in[i];
bram2_data[1].numbers_in[i] = -bram2_data[1].numbers_in[i];
bram2_data[2].numbers_in[i] = -bram2_data[2].numbers_in[i];
}
}

// 配置DMA发送描述符
txring = XAxiDma_GetTxRing(&xaxidma);
n = XAxiDma_BdRingCntCalc(XAXIDMA_BD_MINIMUM_ALIGNMENT, sizeof(bram2_bdringbuf->txbuf));
ret = XAxiDma_BdRingCreate(txring, (uintptr_t)bram2_bdringbuf->txbuf, (uintptr_t)bram2_bdringbuf->txbuf, XAXIDMA_BD_MINIMUM_ALIGNMENT, n);
if (ret != XST_SUCCESS)
{
printf("XAxiDma_BdRingCreate(txring) failed! ret=%d\n", ret);
goto err;
}
printf("BdRing Tx count: %d\n", n);

ret = XAxiDma_BdRingAlloc(txring, 3, &bd);
if (ret != XST_SUCCESS)
{
printf("XAxiDma_BdRingAlloc(txring) failed! ret=%d\n", ret);
goto err;
}

p = bd;
for (i = 0; i {
XAxiDma_BdSetBufAddr(p, (uintptr_t)bram2_data[i].numbers_in);
XAxiDma_BdSetLength(p, sizeof(bram2_data[i].numbers_in), txring->MaxTransferLen);
XAxiDma_BdSetCtrl(p, XAXIDMA_BD_CTRL_TXSOF_MASK | XAXIDMA_BD_CTRL_TXEOF_MASK);
XAxiDma_BdSetId(p, i);
p = (XAxiDma_Bd *)XAxiDma_BdRingNext(txring, p);
}

ret = XAxiDma_BdRingToHw(txring, 3, bd);
if (ret != XST_SUCCESS)
{
printf("XAxiDma_BdRingToHw(txring) failed! ret=%d\n", ret);
goto err;
}

// 配置DMA接收描述符
rxring = XAxiDma_GetRxRing(&xaxidma);
n = XAxiDma_BdRingCntCalc(XAXIDMA_BD_MINIMUM_ALIGNMENT, sizeof(bram2_bdringbuf->rxbuf));
ret = XAxiDma_BdRingCreate(rxring, (uintptr_t)bram2_bdringbuf->rxbuf, (uintptr_t)bram2_bdringbuf->rxbuf, XAXIDMA_BD_MINIMUM_ALIGNMENT, n);
if (ret != XST_SUCCESS)
{
printf("XAxiDma_BdRingCreate(rxring) failed! ret=%d\n", ret);
goto err;
}
printf("BdRing Rx count: %d\n", n);

ret = XAxiDma_BdRingAlloc(rxring, 3, &bd);
if (ret != XST_SUCCESS)
{
printf("XAxiDma_BdRingAlloc(rxring) failed! ret=%d\n", ret);
goto err;
}

p = bd;
for (i = 0; i {
XAxiDma_BdSetBufAddr(p, (uintptr_t)bram2_data[i].numbers_out);
XAxiDma_BdSetLength(p, sizeof(bram2_data[i].numbers_out), rxring->MaxTransferLen);
XAxiDma_BdSetCtrl(p, 0);
XAxiDma_BdSetId(p, i);
p = (XAxiDma_Bd *)XAxiDma_BdRingNext(rxring, p);
}

ret = XAxiDma_BdRingToHw(rxring, 3, bd);
if (ret != XST_SUCCESS)
{
printf("XAxiDma_BdRingToHw(rxring) failed! ret=%d\n", ret);
goto err;
}

// 开始发送数据
ret = XAxiDma_BdRingStart(txring);
if (ret != XST_SUCCESS)
{
printf("XAxiDma_BdRingStart(txring) failed! ret=%d\n", ret);
goto err;
}

// 开始接收数据
ret = XAxiDma_BdRingStart(rxring);
if (ret != XST_SUCCESS)
{
printf("XAxiDma_BdRingStart(rxring) failed! ret=%d\n", ret);
goto err;
}

// 等待收发结束
n = 0;
while (n {
// 检查发送是否结束
ret = XAxiDma_BdRingFromHw(txring, XAXIDMA_ALL_BDS, &bd);
if (ret != 0)
{
n += ret;
p = bd;
for (i = 0; i {
printf("DMA Tx%lu Complete!\n", XAxiDma_BdGetId(p));
p = (XAxiDma_Bd *)XAxiDma_BdRingNext(txring, p);
}

ret = XAxiDma_BdRingFree(txring, ret, bd);
if (ret != XST_SUCCESS)
printf("XAxiDma_BdRingFree(txring) failed! ret=%d\n", ret);
}

// 检查接收是否结束
ret = XAxiDma_BdRingFromHw(rxring, XAXIDMA_ALL_BDS, &bd);
if (ret != 0)
{
n += ret;
p = bd;
for (i = 0; i {
printf("DMA Rx%lu Complete!\n", XAxiDma_BdGetId(p));
p = (XAxiDma_Bd *)XAxiDma_BdRingNext(rxring, p);
}

ret = XAxiDma_BdRingFree(rxring, ret, bd);
if (ret != XST_SUCCESS)
printf("XAxiDma_BdRingFree(rxring) failed! ret=%d\n", ret);
}
}

err:
for (i = 0; i printf("numbers_out[%d]=%f,%f,%f\n", i, bram2_data[0].numbers_out[i], bram2_data[1].numbers_out[i], bram2_data[2].numbers_out[i]);

cleanup_platform();
return 0;
}

程序运行结果:

Hello World
Successfully ran Hello World application
[0] numbers_in=0xc0000000, numbers_out=0xc00000a0
[1] numbers_in=0xc0000140, numbers_out=0xc00001e0
[2] numbers_in=0xc0000280, numbers_out=0xc0000320
BdRing Tx count: 10
BdRing Rx count: 10
DMA Tx0 Complete!
DMA Tx1 Complete!
DMA Tx2 Complete!
DMA Rx0 Complete!
DMA Rx1 Complete!
DMA Rx2 Complete!
numbers_out[0]=19.625000,-8.812500,-169.875000
numbers_out[1]=-39.250000,17.625000,339.750000
numbers_out[2]=58.875000,-26.437500,-509.625000
numbers_out[3]=-78.500000,35.250000,679.500000
numbers_out[4]=98.125000,-44.062500,-849.375000
numbers_out[5]=-117.750000,52.875000,1019.250000
numbers_out[6]=137.375000,-61.687500,-1189.125000
numbers_out[7]=-157.000000,70.500000,1359.000000
numbers_out[8]=176.625000,-79.312500,-1528.875000
numbers_out[9]=-196.250000,88.125000,1698.750000
numbers_out[10]=215.875000,-96.937500,-1868.625000
numbers_out[11]=-235.500000,105.750000,2038.500000
numbers_out[12]=255.125000,-114.562500,-2208.375000
numbers_out[13]=-274.750000,123.375000,2378.250000
numbers_out[14]=294.375000,-132.187500,-2548.125000
numbers_out[15]=-314.000000,141.000000,2718.000000
numbers_out[16]=333.625000,-149.812500,-2887.875000
numbers_out[17]=-353.250000,158.625000,3057.750000
numbers_out[18]=372.875000,-167.437500,-3227.625000
numbers_out[19]=-392.500000,176.250000,3397.500000
numbers_out[20]=412.125000,-185.062500,-3567.375000
numbers_out[21]=-431.750000,193.875000,3737.250000
numbers_out[22]=451.375000,-202.687500,-3907.125000
numbers_out[23]=-471.000000,211.500000,4077.000000
numbers_out[24]=490.625000,-220.312500,-4246.875000
numbers_out[25]=-510.250000,229.125000,4416.750000
numbers_out[26]=529.875000,-237.937500,-4586.625000
numbers_out[27]=-549.500000,246.750000,4756.500000
numbers_out[28]=569.125000,-255.562500,-4926.375000
numbers_out[29]=-588.750000,264.375000,5096.250000
numbers_out[30]=608.375000,-273.187500,-5266.125000
numbers_out[31]=-628.000000,282.000000,5436.000000
numbers_out[32]=647.625000,-290.812500,-5605.875000
numbers_out[33]=-667.250000,299.625000,5775.750000
numbers_out[34]=686.875000,-308.437500,-5945.625000
numbers_out[35]=-706.500000,317.250000,6115.500000
numbers_out[36]=726.125000,-326.062500,-6285.375000
numbers_out[37]=-745.750000,334.875000,6455.250000
numbers_out[38]=765.375000,-343.687500,-6625.125000
numbers_out[39]=-785.000000,352.500000,6795.000000

审核编辑:符乾江

声明:本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人,不代表电子发烧友网立场。文章及其配图仅供工程师学习之用,如有内容侵权或者其他违规问题,请联系本站处理。 举报投诉
  • FPGA
    +关注

    关注

    1603

    文章

    21328

    浏览量

    593251
  • Xilinx
    +关注

    关注

    70

    文章

    2121

    浏览量

    119388
收藏 人收藏

    评论

    相关推荐

    Xilinx高性能PCIe DMA控制器IP,8个DMA通道

    或Scather Gather DMA,提供FIFO/AXI4-Stream用户接口。 基于PCI Express Integrated Block,Multi-Channel PCIe RDMA
    的头像 发表于 02-22 11:11 312次阅读
    <b class='flag-5'>Xilinx</b>高性能PCIe <b class='flag-5'>DMA</b>控制器<b class='flag-5'>IP</b>,8个<b class='flag-5'>DMA</b>通道

    XILINX FPGA IPAXI Traffic Generator

    AXI Traffic Generator IP 用于在AXI4和AXI4-Stream互连以及其他AXI4系统外设上生成特定序列(流量)。
    的头像 发表于 11-23 16:03 828次阅读
    <b class='flag-5'>XILINX</b> <b class='flag-5'>FPGA</b> <b class='flag-5'>IP</b>之<b class='flag-5'>AXI</b> Traffic Generator

    FPGAIP学习的正确打开方式

    的情况时,总会遇到一些以前未曾接触过的新内容,这些新内容会让我们感到陌生和恐惧,不知道该如何下手。 那么今天以xilinx vivado 为例分享学习FPGAIP的正确打开方式
    发表于 11-17 11:09

    AXI传输数据的过程

    AXI4为例,有AXI full/lite/stream之分。 在Xilinx系列FPGA及其有关IP核中,经常见到
    的头像 发表于 10-31 15:37 469次阅读
    <b class='flag-5'>AXI</b>传输数据的过程

    LogiCORE JTAG至AXI Master IP核简介

    LogiCORE JTAG至AXI Master IP核是一个可定制的核,可生成AXIAXI总线可用于处理和驱动系统中FPGA内部的AXI信号。AX
    的头像 发表于 10-16 10:12 481次阅读
    LogiCORE JTAG至<b class='flag-5'>AXI</b> Master <b class='flag-5'>IP</b>核简介

    什么是AXIAXI如何工作?

    Xilinx 从 Spartan-6 和 Virtex-6 器件开始采用高级可扩展接口 (AXI) 协议作为知识产权 (IP) 内核。Xilinx 继续将
    的头像 发表于 09-27 09:50 691次阅读
    什么是<b class='flag-5'>AXI</b>?<b class='flag-5'>AXI</b>如何工作?

    LogiCORE IP AXI4-Stream FIFO内核解决方案

    LogiCORE IP AXI4-Stream FIFO内核允许以内存映射方式访问一个AXI4-Stream接口。该内核可用于与AXI4-Stream
    的头像 发表于 09-25 10:55 601次阅读
    LogiCORE <b class='flag-5'>IP</b> <b class='flag-5'>AXI</b>4-Stream FIFO内核解决方案

    XILINX FPGA IP之FIFO Generator例化仿真

    上文XILINX FPGA IP之FIFO对XILINX FIFO Generator IP的特性和内部处理流程进行了简要的说明,本文通过实
    的头像 发表于 09-07 18:31 912次阅读
    <b class='flag-5'>XILINX</b> <b class='flag-5'>FPGA</b> <b class='flag-5'>IP</b>之FIFO Generator例化仿真

    基于AXI总线的DDR3读写测试

    本文开源一个FPGA项目:基于AXI总线的DDR3读写。之前的一篇文章介绍了DDR3简单用户接口的读写方式:《DDR3读写测试》,如果在某些项目中,我们需要把DDR挂载到AXI总线上,
    的头像 发表于 09-01 16:20 2290次阅读
    基于<b class='flag-5'>AXI</b>总线的DDR3读写测试

    基于Xilinx FPGA AXI-EMC IP的EMIF通信测试

    外部存储器接口( EMIF )通信常用于FPGA和DSP之间的数据传输,即将FPGA作为DSP的外部SRAM、或者协同处理器等。Xilinx提供了AXI-EMC
    的头像 发表于 08-31 11:25 2812次阅读
    基于<b class='flag-5'>Xilinx</b> <b class='flag-5'>FPGA</b> <b class='flag-5'>AXI</b>-EMC <b class='flag-5'>IP</b>的EMIF通信测试

    自定义AXI-Lite接口的IP及源码分析

    在 Vivado 中自定义 AXI4-Lite 接口的 IP,实现一个简单的 LED 控制功能,并将其挂载到 AXI Interconnect 总线互联结构上,通过 ZYNQ 主机控制
    发表于 06-25 16:31 2053次阅读
    自定义<b class='flag-5'>AXI</b>-Lite接口的<b class='flag-5'>IP</b>及源码分析

    Xilinx FPGA AXI4总线(一)介绍【AXI4】【AXI4-Lite】【AXI-Stream】

    FPGA 应用角度看看 AMBA 总线中的 AXI4 总线。
    发表于 06-21 15:21 1877次阅读
    <b class='flag-5'>Xilinx</b> <b class='flag-5'>FPGA</b> <b class='flag-5'>AXI</b>4总线(一)介绍【<b class='flag-5'>AXI</b>4】【<b class='flag-5'>AXI</b>4-Lite】【<b class='flag-5'>AXI</b>-Stream】

    简单讲解AXI Interconnect IP核的使用方法

    最近需要用到AXI接口的模块,xilinxIP核很多都用到了AXI总线进行数据和指令传输。如果有多个设备需要使用AXI协议对
    的头像 发表于 06-19 15:45 5381次阅读
    <b class='flag-5'>简单</b>讲解<b class='flag-5'>AXI</b> Interconnect <b class='flag-5'>IP</b>核的使用方法

    XILINX FPGA IP之Clocking Wizard详解

    锁相环基本上是每一个fpga工程必不可少的模块,之前文档xilinx 7 系列FPGA时钟资源对xilinx fpga的底层时钟资源做过说明
    发表于 06-12 17:42 3275次阅读
    <b class='flag-5'>XILINX</b> <b class='flag-5'>FPGA</b> <b class='flag-5'>IP</b>之Clocking Wizard详解

    Video In to AXI4-Stream IP核知识介绍

    大家好!今日分享一些关于Video In to AXI4-Stream IP 核的知识。在具体学习IP核的过程中,我也将分享一些关于如何看xilinx英文文档的技巧。
    的头像 发表于 05-18 14:55 1060次阅读
    Video In to <b class='flag-5'>AXI</b>4-Stream <b class='flag-5'>IP</b>核知识介绍