• AD9833
• AD9834
• AD9837
• AD9838

• CN0156

• EVAL-AD9833SDZ
• EVAL-AD9834SDZ
• EVAL-AD9837SDZ
• EVAL-AD9838SDZ

This is a Linux industrial I/O (IIO) subsystem driver, targeting serial interface DDS controllers. The industrial I/O subsystem provides a unified framework for drivers for many different types of converters and sensors using a number of different physical interfaces (i2c, spi, etc). See IIO for more information.

In the example below, it's assumed that spi0 is the SPI controller to which the AD983X is attached to. Typically, these are defined in the board device-tree where the AD983X is attached to.

	&spi0 {
		#address-cells = <1>;
		#size-cells = <0>;
		status = "okay";
 
		ad9833@0{
			#clock-cells = <0>;
			compatible = "adi,ad9833";
			reg = <0>;
			spi-max-frequency = <1000000>;
			spi-cpol;
			clocks = <&osc>;
			vcc-supply = <&vcc>;
		};
	};

This example also references a regulator (vcc-supply) and a clock (osc). These can be left out, in which case it's assumed they are somehow hard-wired on the board to a proper voltage supply and clock source.

The compabtible string can be any of the following:

• adi,ad9833
• adi,ad9834
• adi,ad9837
• adi,ad9838

Note that, the *adi,* prefix can be omitted and this still works. It is preferred to be added to avoid any potential collisions with other drivers from other vendors.

However, the voltage supply & clock can be defined via device-tree as well. See example below:

	/ {
		vcc: fixedregulator@0 {
			compatible = "regulator-fixed";
			regulator-name = "fixed-supply";
			regulator-min-microvolt = <2500000>;
			regulator-max-microvolt = <2500000>;
			regulator-boot-on;
		};
 
		osc: oscillator {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <25000000>;
		};
	};

This assumes that the board has the chips & drivers to generate voltages like this & clock frequencies.

Configure kernel with “make menuconfig” (alternatively use “make xconfig” or “make qconfig”)

Linux Kernel Configuration
	Device Drivers  --->
		[*] Staging drivers  --->
			<*>     Industrial I/O support --->
			    --- Industrial I/O support
			    -*-   Enable ring buffer support within IIO
			    -*-     Industrial I/O lock free software ring
			    -*-   Enable triggered sampling support

			          *** Direct Digital Synthesis ***
			    [--snip--]

			    <*>   Analog Devices ad9833/4/ driver

			    [--snip--]

/sys/bus/iio/devices/…/ddsX_freqY_scale

Scale to be applied to ddsX_freqY in order to obtain the desired value in Hz. If shared across all frequency registers Y is not present. It is also possible X is not present if shared across all channels.

root:/sys/devices/platform/bfin-spi.0/spi0.3/device0> cat dds0_freq_scale
1

/sys/bus/iio/devices/…/ddsX_freqY

Stores frequency into tuning word Y. There will be more than one ddsX_freqY file, which allows for pin controlled FSK Frequency Shift Keying (ddsX_pincontrol_freq_en is active) or the user can control the desired active tuning word by writing Y to the ddsX_freqsymbol file.

root:/sys/devices/platform/bfin-spi.0/spi0.3/device0> echo 1000000 > dds0_freq0
root:/sys/devices/platform/bfin-spi.0/spi0.3/device0> echo 500000 > dds0_freq0

freq0 = ddsX_freq0 * dds0_freq_scale = 1000000 * 1 = 1 MHz
freq1 = ddsX_freq1 * dds0_freq_scale = 500000 * 1 = 500 kHz

/sys/bus/iio/devices/…/ddsX_phaseY_scale

Scale to be applied to ddsX_phaseY in order to obtain the desired value in rad. If shared across all phase registers Y is not present. It is also possible X is not present if shared across all channels.

root:/sys/devices/platform/bfin-spi.0/spi0.3/device0> cat dds0_phase_scale
0.0015339808

/sys/bus/iio/devices/…/ddsX_phaseY

Stores phase into Y. There will be more than one ddsX_phaseY file, which allows for pin controlled PSK Phase Shift Keying (ddsX_pincontrol_phase_en is active) or the user can control the desired phase Y which is added to the phase accumulator output by writing Y to the en_phase file.

root:/sys/devices/platform/bfin-spi.0/spi0.3/device0> echo 512 > dds0_phase0
root:/sys/devices/platform/bfin-spi.0/spi0.3/device0> echo 2048 > dds0_phase0

phase0 = dds0_phase0 * ddsX_phaseY_scale = 512 * 0.0015339808 = 0.7853981696 rad
phase1 = dds0_phase1 * ddsX_phaseY_scale = 2048 * 0.0015339808 = PI = 3.1415926 rad

/sys/bus/iio/devices/…/ddsX_outY_wavetype_available

Lists all available output waveform options.

root:/sys/devices/platform/bfin-spi.0/spi0.3/device0> cat dds0_out0_wavetype_available
sine triangle

/sys/bus/iio/devices/…/ddsX_outY_wavetype

Specifies the output waveform. (sine, triangle, ramp, square, …) For a list of available output waveform options read available_output_modes.

root:/sys/devices/platform/bfin-spi.0/spi0.3/device0> echo sine > dds0_out0_wavetype

/sys/bus/iio/devices/…/ddsX_pincontrol_en

ddsX_pincontrol_en: Both, the active frequency and phase is controlled by the respective phase and frequency control inputs. In case the device in question allows to independent controls, then there are dedicated files (ddsX_pincontrol_freq_en, ddsX_pincontrol_phase_en).

root:/sys/devices/platform/bfin-spi.0/spi0.3/device0> echo 0 > dds0_pincontrol_en

/sys/bus/iio/devices/…/ddsX_out_enable
/sys/bus/iio/devices/…/ddsX_outY_enable

ddsX_outY_enable controls signal generation on output Y of channel X. Y may be suppressed if all channels are controlled together.

root:/sys/devices/platform/bfin-spi.0/spi0.3/device0> echo 1 > dds0_out_enable

/sys/bus/iio/devices/…/ddsX_freqsymbol

Specifies the active output frequency tuning word. The value corresponds to the Y in ddsX_freqY. To exit this mode the user can write ddsX_pincontrol_freq_en or ddsX_out_enable file.

root:/sys/devices/platform/bfin-spi.0/spi0.3/device0> echo 1 > dds0_freqsymbol
root:/sys/devices/platform/bfin-spi.0/spi0.3/device0> echo 0 > dds0_freqsymbol
root:/sys/devices/platform/bfin-spi.0/spi0.3/device0>