The AD9649 is a 14-bit, monolithic, single channel analog-to-digital converter (ADC) with a conversion rate of up to 80MSPS. This reference design includes the device data capture and SPI interface. The samples are written to the external DDR-DRAM on KC705. It allows programming the device and monitoring it's internal registers via SPI. The board also provides other options to drive the clock to the ADC.

• AD9649-Evaluation Board
• High Speed ADC FMC Interposer

• KC705

The bit file provided combines the FPGA bit file and the SDK elf files. It may be used for a quick check on the system. All you need is the hardware and a PC running a UART terminal and the programmer (IMPACT).

• KC705 board
• AD9649 evaluation board & Power supply
• ADC FMC interposer board
• Signal/Clock generator

• Xilinx ISE (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
• A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.

• Download the gzip file and extract the sw/cf_ad9649_ebz.bit file.

To begin make the following connections (see image below):

• Connect the AD9649 evaluation board to the FMC Interposer board.
• Connect the interposer board to the FMC-LPC connector of KC705 board.
• Connect power to KC705 and the AD9649 evaluation boards.
• Connect two USB cables from the PC to the JTAG and UART USB connectors on KC705.
• Follow the AD9649 evaluation board setup instructions.

After the hardware setup, turn the power on to the KC705 and the AD9649 evaluation boards.

Start IMPACT, and initialze the JTAG chain. The program should recognize the Kintex 7 device. Start a UART terminal (set to 57600 baud rate) and then program the device. If programming was successful, you should be seeing messages appear on the terminal as shown in figure below. After programming the AD9649, the program checks data capture on various test modes.

A chipscope bus plot of the captured input is shown below.

The reference design consists of two functional modules, a capture interface and a DMA interface. The capture interface provides the physical interface to the ADC. It is then transferred to the DMA module. The DMA module interfaces to the Xilinx AXI-DMA engine and stores a programmable number of samples on the external DDR-DRAM on KC705.

See the regmap.txt file inside the pcores.

FPGA Referece Designs:

Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See generating Xilinx netlist/verilog files from xco files for details.

The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to Xilinx EDK documentation for details.

• VITA's FMC info
• ask questions about the FPGA reference design