The AD9122 is a dual 16-bit, high dynamic range, digital-to-analog converter (DAC) that provides a sample rate of 1200MSPS. This reference design includes two DDS generators that drives both channels of the device. The programming is done via the USB-SPI interface.

• AD9122 Evaluation Board
• DAC FMC Interposer Board

• ML605

The bit file provided combines the FPGA bit file and the SDK elf files. It may be used for a quick check on the system. All you need is the hardware and a PC running a UART terminal, ADI DAC software and the programmer (IMPACT).

• ML605 board
• AD9122-M537x-EBZ board & Power supply
• DAC FMC interposer board
• Signal/Clock generator (1GHz)
• Spectrum Analyzer

• Xilinx ISE 13.2 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
• A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.
• ADI DPG DAC Software Suite available here.

• Download the gzip file and extract the sw/cf_ad9122_ebz.bit file.

To begin make the following connections (see image below):

• Connect the AD9122-M537x-EBZ board to the FMC Interposer board.
• Connect the interposer board to the FMC-LPC connector of ML605 board.
• Connect power to ML605 and the AD9122-M537x-EBZ boards.
• Connect two USB cables from the PC to the JTAG and UART USB connectors on ML605.
• Connect a USB cable to the AD9122-M537x-EBZ board.
• Connect an external clock source to AD9122-M537x-EBZ board's J1 SMA connector.
• Connect two spectrum analyzers to AD9122-M537x-EBZ board's J3 and J8 SMA connectors.

Setup the clock source to be 1GHz. After the hardware setup, turn the power on to the ML605 and the AD9122-M537x-EBZ boards.

Start ADI- AD9122 SPI program (see screenshot below)-

• (1) change the interpolation to 2x.
• (2) click on “Run Forever” button.

Start IMPACT, and initialze the JTAG chain. The program should recognize the Virtex 6 device (see screenshot below). Start a UART terminal (set to 57600 baud rate) and then program the device.

If programming was successful, you should be seeing messages appear on the terminal as shown in figure below.

After DDS is enabled, you should see the spectrum analyzer displaying the two tones (90MHz and 70MHz).

The reference design consists of two independent DDS modules and a lvds interface.

The DDS module consists of a Xilinx IP core and a DDR-DDS. Internally the DDS runs at fDAC/3 clock. The DDR-DDS allows any pattern to be generated in the memory to be driven to the DAC. The output samples are interleaved and driven by the lvds interface.

Please see the regmap.txt file in the pcore directory.

FPGA Referece Designs:

Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See generating Xilinx netlist/verilog files from xco files for details.

The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to Xilinx EDK documentation for details.

• VITA's FMC info
• Ask questions about the FPGA reference design