A 0.8-V 1-MSs 10-bit SAR ADC f

　　SAR开关时序

　　Abstract—This paper presents a 10-bit single-ended SAR ADC suitable for multi-channel neural recording. The proposed ADC introduces several power saving techniques to boost the energy efficiency. The ADC is built with on-chip common-mode buffer for input tracking， which is reused as the pre-amplifier of a current-mode comparator during conversion. A small capacitor is inserted between the amplifier and the capacitive DAC array in order to reduce the capacitive load on the amplifier. A split capacitor array with dual thermometer decoders is proposed to reduce the switching energy. Implemented in 0.13- CMOS technology， the ADC achieved a maximum differential nonlinearity （DNL） of 0.33/ 0.56 LSB， maximum integral nonlinearity （INL） of 0.61/ 0.55 LSB， effective number-of-bits （ENOB） of 8.8， and a power consumption of 9- W。

　　Index Terms—ADC， analog-to-digital converter， low power， low voltage， multi-channel， SAR， successive approximation。