PCI设计指南

Chapter 1 Getting Started
Other Documentation  1-1
Technical Support  1-2
Chapter 2 Signal Description
PCI Bus Interface Signals  2-2
User Interface Signals 2-10
Special Requirements  2-23
Chapter 3 General Design Guidelines
Design Steps 3-1
Target Designs 3-1
Initiator Designs  3-2
Burst Designs 3-2
Advanced Designs  3-2
Know the Degree of Difficulty 3-2
Understand Signal Pipelining  3-3
Keep it Registered 3-4
Recognize Timing Critical Signals 3-5
Use Supported Design Flows 3-5
Make Only Allowed Modifications  3-6
Chapter 4 Customizing the LogiCORE PCI Interface
Using the Web-Based PCI Configuration Tool 4-1
Editing the Configuration File  4-1
Constant Declarations 4-2
Device and Vendor ID 4-2
Class Code and Revision ID  4-3
Subsystem Vendor ID and Subsystem ID 4-3
Base Address Registers  4-4
Target Extension Signals  9-1
Handling 64-bit Transfers 9-2
Chapter 10 Target Only Designs
Logic Design Considerations  10-1
System Level Considerations 10-2
Chapter 11 Initiator Design Tips
Determine the Required Transfers 11-1
Determine Termination Behavior  11-1
Determine Transaction Ordering Rules. 11-2
Assemble the Design  11-2
Chapter 12 Initiator Data Transfer and Control
Typical Initiator Data Interface  12-1
Initiator Interface Signals. 12-2
Initiator Control 12-3
Inputs to the State Machine . 12-5
The State Machine. 12-6
Outputs to the PCI Interface  12-10
Data Register Control Signals 12-12
Sample Transactions  12-12
Chapter 13 Initiator Data Phase Control
Control Modes. 13-1
Control Pipeline. 13-4
Transaction Termination Rules . 13-4
Implementation 13-5
Sample Transactions  13-7
Chapter 14 Initiator Burst Transfers
Keeping Track of the Address Pointer  14-1
Sinking Data in Burst Transfers  14-2
Sourcing Data in Burst Transfers  14-3
Design Example  14-5
Inputs to the State Machine . 14-8
The State Machine. 14-10
Outputs to the PCI Interface  14-13
Control Signals. 14-17
Sample Transactions  14-17