基于FPGA的神经网络自整定PID控制器设计

基于FPGA 的神经网络自整定PID 控制器设计
The De ign of Neural Network Self_Tuning PlD Controller Ba ed on FPGA

摘要本文基于FPGA（现场可编程门阵列）技术实现了改进的BP 网络自整定PID 控制器的设计。首先，采用MATLAB 设计控制器，针对特定被控对象模型，在闭环控制系统中通过改进的BP 网络算法训练神经网络，获得比较理想的系统输出；依据训练好的网络权值，在FPGA 集成开发环境下，基于VHDL（甚高速集成电路硬件描述语言）设计BP 网络自整定PID 控制器，完成时序仿真测试，并在一种具体的FPGA 器件上实现。实验表明，其设计过程合理，实现结果正确，适合于采用复杂智能控制策略并要求实时性、快速性的单片或小型控制系统。
关键词改进的BP 网络自整定PID 控制器VHDL FPGA
Abstract In this paper，an improved BP neural network self-tuning PID controller based on FPGA（Field Programmable Data Array）is designed. At first，the controller is designed in MATLAB，the neural network is trained with the improved BP algorithm based on the given object model in the closed loop control system to take the perfect system output. Depending on the network weights，the BP neural network self-tuning PID controller based on VHDL（Very high speed integrated circuit Hardware Description Language）is designed under the FPGA integration development environment，then its timing simulation and its implementation at the FPGA device are completed. The experiment indicates that the design process is reasonable and the test result is accurate. The controller is fit to implement intelligent control strategy on the real-time basis，as well as fast and single-chip or small control system.
Keywords Improved BP neural network Self-tuning PID controller VHDL FPGA