25AA010A/25LC010A/25AA320A/25L

25AA010A/25LC010A 25AA320A/25LC320A
25AA020A/25LC020A 25AA640A/25LC640A*
25AA040A/25LC040A 25AA128/25LC128
25AA080A/25LC080A 25AA256/25LC256
25AA080B/25LC080B 25AA512/25LC512*
25AA160A/25LC160A 25AA1024/25LC1024*
25AA160B/25LC160B

Microchip Technology Inc. supports the Serial Peripheral
Interface (SPI) compatible serial bus architecture
with low-voltage serial Electrically Erasable PROMs
(EEPROM) that range in density from 1 Kbits up to 1
Mbits. Byte-level and page-level functions are supported,
but the higher density 512 Kbit and 1 Mbit
devices also feature Sector and Chip erase functions
typically associated with Flash-based products.
The bus signals required are a clock input (SCK) plus
separate data in (SI) and data out (SO) lines. Access to
the device is controlled through a Chip Select (CS)
input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused, transitions
on its inputs will be ignored, with the exception of
Chip Select, allowing the host to service higher priority
interrupts.
The entire series of SPI compatible devices are available
in the standard 8-lead PDIP and SOIC packages,
as well as the more advanced packages such
as the 8-lead TSSOP, MSOP, 2x3 DFN, 5x6 DFN and
6-lead SOT-23. All packages are RoHS compliant
with a Pb-free (Matte Tin) finish.