基于CPLD的频率键控系统设计的研究

现代通信系统要求通信距离远、通信容量大、传输质量好。作为其关键技术之一的调
制解调技术一直是人们研究的一个重要方向。本论文主要讨论和仿真了基于CPLD 的FSK、4FSK 系统单元设计，并对调制解调系统和CPLD 设计方法进行了相关的研究。以VHDL 作 为设计的硬件描述语言，在Altera 公司的Maxplus2 开发平台上进行了程序设计及波形仿真。对各个模块进行CPLD 的建模，然后对各个模块的设计内容进行了层层细化，最终达到模块的具体软硬件实现。
关键词：频率键控系统、CPLD、VHDL
Abstract: Long distance, large capability and high quality of transmission are required in modern communication system. Modulation and demodulation, which is one of the most key techniques in communication, has been always an important aspect people research. This thesis primarily focused on the modulation and demodulation system and the design technique of CPLD, and also discussed and simulated the digitalized FSK、4FSK systems based on CPLD. The author utilized VHDL to be the hardware describing language of design and has been waveform simulated on the basis of a CPLD development platform Maxplus2 developed by Altera. “TOP-TO-DOWN” is the main feature of this design. CPLD modeling has firstly been done for each module of system, then the design content divided into smaller parts layer to layer, and finally achieved both in hardware and software in details. The whole program has passed the hardware debugging on CPLD experiment exploitation board which takes EPM7128SLC84-7 to be the main chip.
KeyWords: FSK; CPLD; VHDL