基于FPGA/CPLD的LED/LCD通用显示译码器设计

基于FPGA/CPLD的LED/LCD通用显示译码器设计
Design of Commonly Used LED/LCD Display Decoder Based on FPGA/CPLD

摘要:各种数字系统的终端设备都需要对十进制信息进行数码显示，而LED和LCD是最常用的显示器件。在大规模可编程逻辑器件FPGA与CPLD的硬件基础上，根据显示译码器原理运用VHDL硬件描述语言对LED/LCD的通用七段显示译码器进行了设计，同时使用QUARTUS 1开发软件对设计电路进行了时序仿真和功能验证。此设计在大规模数字电路的数码显示中更为实用，具有设计简单、使用灵活和工作可靠等优点。
关键词:译码器仿真VHDL描述数字电路脉冲信号
Abstract; Digital display of decimal information is needed for all kinds of terminal equipments of digital systems, and LED and LCD are the most common display devices. On the hardware basis of large-scale programmable logical devices FPGA and CPLD, and by using hardware description language VHDL, the seven-segment display decoder for LED/LCD is designed. In addition, with QUARTUS 11 developing software,the timing simulation and functional verification of the designed circuit are carried out. The design can be used practicaly in digital display of large-scale digital circuits. This device features simple design, flexible and reliable operation.
Keywords;D ecoder Simulation VHDLd escription Digitalc ircuit Pulses ignal