AM3892 Sitara 处理器

数据： AM389x Sitara ARM Microprocessors (MPUs) 数据表

描述

AM389x Sitara ARM处理器是一个高度集成的可编程平台，利用TI的Sitara技术来满足以下应用的处理需求：单板计算，网络和通信处理，工业自动化，人机界面和交互式服务点信息亭。

该设备使原始设备制造商（OEM）和原始设计制造商（ODM）能够快速实现市场设备具有强大的操作系统支持，丰富的用户界面和高处理性能，通过完全集成的混合处理器解决方案的最大灵活性。该器件将高性能ARM 处理与高度集成的外设集合在一起。

具有NEON浮点扩展的ARM Cortex-A8 32位RISC处理器包括：32KB指令缓存; 32KB的数据缓存; 256KB的L2缓存;和64KB的RAM。

丰富的外设集可以控制外部外围设备并与外部处理器通信。有关每个外围设备的详细信息，请参阅本文档中的相关章节以及相关的外围设备参考指南。外围设备包括：高清视频处理子系统（HDVPSS），提供同步高清和标清模拟视频输出和双高清视频输入;最多两个千兆以太网MAC（10 Mbps，100 Mbps，1000 Mbps），带有GMII和MDIO接口;两个USB端口，集成2.0 PHY; PCIe端口x2通道符合GEN2标准接口，允许设备充当PCIe根复合体或设备端点;一个6声道McASP音频串口（带DIT模式）;两个双通道McASP音频串口（带DIT模式）;一个McBSP多通道缓冲串口;三个支持IrDA和CIR的UART; SPI串行接口; SD和SDIO串行接口;两个I ² C主从接口;最多64个GPIO引脚;七个32位定时器;系统看门狗定时器;双DDR2和DDR3 SDRAM接口;灵活的8位和16位异步存储器接口;最多两个SATA接口，可通过端口倍增器在两个或更多磁盘驱动器上进行外部存储。

该设备还包括一个SGX530 3D图形引擎（仅在AM3894设备上可用），以关闭从核心加载许多视频和图像处理任务。此外，该设备还有一套完整的ARM开发工具，包括C编译器和Microsoft Windows调试器界面，可以查看源代码执行情况。

设备包已经采用Via Channel技术专门设计。该技术允许在这种0.65 mm间距封装中使用0.8 mm间距PCB特征尺寸，从而大幅降低PCB成本。由于Via Channel BGA技术的层效率提高，Via Channel技术还允许仅在两个信号层中进行PCB布线。

特性

High-Performance Sitara ARM Microprocessors (MPUs)
- ARMCortex-A8 RISC Processor
  - Up to 1.20 GHz
ARM Cortex-A8 Core
- ARMv7 Architecture
  - In-Order, Dual-Issue, Superscalar Processor Core
  - NEON Multimedia Architecture
- Supports Integer and Floating Point (VFPv3-IEEE754 Compliant)
  - Jazelle RCT Execution Environment
ARM Cortex-A8 Memory Architecture
- 32-KB Instruction and Data Caches
- 256-KB L2 Cache
- 64-KB RAM, 48-KB of Boot ROM
512KB of On-Chip Memory Controller (OCMC) RAM
SGX530 3D Graphics Engine (Available Only on the AM3894 Device)
- Delivers up to 30 MTriangles per Second
- Universal Scalable Shader Engine
- Direct3D Mobile, OpenGL ES 1.1 and 2.0, OpenVG 1.1, OpenMax API Support
- Advanced Geometry DMA Driven Operation
- Programmable HQ Image Anti-Aliasing
Endianness
- ARM Instructions and Data – Little Endian
HD Video Processing Subsystem (HDVPSS)
- Two 165-MHz HD Video Capture Channels
  - One 16-Bit or 24-Bit and One 16-Bit Channel
  - Each Channel Splittable Into Dual 8-Bit Capture Channels
- Two 165-MHz HD Video Display Channels
  - One 16-Bit, 24-Bit, 30-Bit Channel and One 16-Bit Channel
- Simultaneous SD and HD Analog Output
- Digital HDMI 1.3 Transmitter with PHY with HDCP up to 165-MHz Pixel Clock
- Three Graphics Layers
Dual 32-Bit DDR2 and DDR3 SDRAM Interfaces
- Supports up to DDR2-800 and DDR3-1600
- Up to Eight x8 Devices Total
- 2GB of Total Address Space
- Dynamic Memory Manager (DMM)
  - Programmable Multi-Zone Memory Mapping and Interleaving
  - Enables Efficient 2D Block Accesses
  - Supports Tiled Objects in 0°, 90°, 180°, or 270° Orientation and Mirroring
  - Optimizes Interlaced Accesses
One PCI Express (PCIe) 2.0 Port with Integrated PHY
- Single Port with 1 or 2 Lanes at 5.0 GT per Second
- Configurable as Root Complex or Endpoint
Serial ATA (SATA) 3.0 Gbps Controller with Integrated PHYs
- Direct Interface for Two Hard Disk Drives
- Hardware-Assisted Native Command Queuing (NCQ) from up to 32 Entries
- Supports Port Multiplier and Command-Based Switching
Two 10 Mbps, 100 Mbps, and 1000 Mbps Ethernet MACs (EMAC)
- IEEE 802.3 Compliant (3.3-V I/O Only)
- MII and GMII Media Independent Interfaces
- Management Data I/O (MDIO) Module
Dual USB 2.0 Ports with Integrated PHYs
- USB 2.0 High-Speed and Full-Speed Client
- USB 2.0 High-Speed, Full-Speed, and Low-Speed Host
- Supports Endpoints 0-15
General-Purpose Memory Controller (GPMC)
- 8-Bit and 16-Bit Multiplexed Address and Data Bus
- Up to 6 Chip Selects with up to 256-MB Address Space per Chip Select Pin
- Glueless Interface to NOR Flash, NAND Flash (with BCH and Hamming Error Code Detection), SRAM and Pseudo-SRAM
- Error Locator Module (ELM) Outside of GPMC to Provide up to 16-Bit and 512-Byte Hardware ECC for NAND
- Flexible Asynchronous Protocol Control for Interface to FPGA, CPLD, ASICs
Enhanced Direct-Memory-Access (EDMA) Controller
- Four Transfer Controllers
- 64 Independent DMA Channels and 8 Quick DMA (QDMA) Channels
Seven 32-Bit General-Purpose Timers
One System Watchdog Timer
Three Configurable UART, IrDA, and CIR Modules
- UART0 with Modem Control Signals
- Supports up to 3.6864 Mbps UART
- SIR, MIR, FIR (4.0 MBAUD), and CIR
One 40-MHz Serial Peripheral Interface (SPI) with Four Chip Selects
SD and SDIO Serial Interface (1-Bit and 4-Bit)
Dual Inter-Integrated Circuit (I²C bus) Ports
Three Multichannel Audio Serial Ports (McASPs)
- One Six-Serializer Transmit and Receive Port
- Two Dual-Serializer Transmit and Receive Ports
- DIT-Capable For SDIF and PDIF (All Ports)
Multichannel Buffered Serial Port (McBSP)
- Transmit and Receive Clocks up to 48 MHz
- Two Clock Zones and Two Serial Data Pins
- Supports TDM, I2S, and Similar Formats
Real-Time Clock (RTC)
- One-Time or Periodic Interrupt Generation
Up to 64 General-Purpose I/O (GPIO) Pins
On-Chip ARM ROM Bootloader (RBL)
Power, Reset, and Clock Management
- SmartReflex Technology (Level 2)
- Seven Independent Core Power Domains
- Clock Enable and Disable Control For Subsystems and Peripherals
IEEE 1149.1 (JTAG) and IEEE 1149.7 (cJTAG) Compatible
Via Channel Technology Enables use of
0.8-mm Design Rules
40-nm CMOS Technology
3.3-V Single-Ended LVCMOS I/Os (Except for DDR3 at 1.5 V, DDR2 at 1.8 V, and DEV_CLKIN at 1.8 V)

参数与其它产品相比 AM3x


Arm MHz (Max.)
Serial I/O
Graphics Acceleration
EMAC
DRAM
Operating Temperature Range (C)
Approx. Price (US$)

AM3892	AM3894
1200	1200
USB I2C McASP McBSP McSPI UART SATA	USB I2C McASP McBSP McSPI UART SATA
	1 3D
10/100/1000	10/100/1000
DDR2 DDR3	DDR2 DDR3
0 to 95	-40 to 105 0 to 95
48.58 \| 1ku	50.99 \| 1ku
无样片	无样片