SpinalHDL语法篇之Bool类型

作为SpinalHDL语法篇的第一节，我们也从最简单的开始。

Bool类型定义

Bool类型就是Verilog中的单bit类型，定义方式如下：

Syntax	Description	Return
Bool()	创建Bool类型变量	Bool
True	创建Bool类型变量，并赋值true	Bool
False	创建Bool类型变量，并赋值false	Bool
Bool(value: Boolean)	创建Bool类型变量，并使用Scala表达式赋值	Bool

Example：

vala=Bool()
valb=True
valc=False
vald=Bool(1>2)

生成的Verilog代码如下：

wirea;
wireb;
wirec;
wired;

assignb=1'b1;
assignc=1'b0;
assignd=1'b0;

逻辑运算

下图为官方的逻辑运算解释，也不翻译了，很容易理解。

Operator	Description	Return type
!x	Logical NOT	Bool
x && y	Logical And	Bool
x & y	Logical And	Bool
x || y	Logical OR	Bool
x | y	Logical OR	Bool
x ^ y	Logical XOR	Bool
x.set[()]	Set x to True	Bool
x.clear[()]	Set x to False	Bool
x.setWhen(cond)	Set x when cond is True	Bool
x.clearWhen(cond)	Clear x when cond is True	Bool
x.riseWhen(cond)	Set x when x is False and cond is True	Bool
x.fallWhen(cond)	Clear x when x is True and cond is True	Bool

vale=a&b
valf=a|b
valg=a^b
valh=!a

vali=Bool()
i.set()
valj=Bool()
j.clear()

valk=True#这里必须有初值，否则下一句会报错
k.clearWhen(b)

vall=True
when(b){
l:=False
}

valm=RegInit(False)#关于寄存器类型，这里先熟悉一下，后面章节会讲到
m.riseWhen(b)

边缘检测

Operator	Description	Return type
x.edge[()]	Return True when x changes state	Bool
x.edge(initAt: bool)	Same as x.edge but with a reset value	Bool
x.rise[()]	Return True when x was low at the last cycle and is now high	Bool
x.rise(initAt: Bool)	Same as x.rise but with a reset value	Bool
x.fall[()]	Return True when x was high at the last cycle and is now low	Bool
x.fall(initAt: Bool)	Same as x.fall but with a reset value	Bool
x.edges[()]	Return a bundle (rise, fall, toggle)	BoolEdges
x.edges(initAt: Bool)	Same as x.edges but with a reset value	BoolEdges

vala=Bool()
valb=False
when(a.edge()){
b:=True
}
valc=a.edge(False)

转换后的代码为：

moduleDemoBool(
inputclk,
inputreset
);

wirea;
regb;
rega_regNext;
wirewhen_DemoBool_l35;
rega_regNext_1;
wirec;

always@(*)begin
b=1'b0;
if(when_DemoBool_l35)begin
b=1'b1;
end
end

assignwhen_DemoBool_l35=(a^a_regNext);
assignc=(a^a_regNext_1);
always@(posedgeclk)begin
a_regNext<= a;
  end

  always @(posedge clk or posedge reset) begin
    if(reset) begin
      a_regNext_1 <= 1'b0;
    end else begin
      a_regNext_1 <= a;
    end
  end

endmodule

valedgeBundle=myBool_2.edges(False)
when(edgeBundle.rise){
//dosomethingwhenarisingedgeisdetected
}
when(edgeBundle.fall){
//dosomethingwhenafallingedgeisdetected
}
when(edgeBundle.toggle){
//dosomethingateachedge
}

数值比对

Operator	Description	Return type
x === y	Equality	Bool
x =/= y	Inequality	Bool

审核编辑：汤梓红