半导体封装测试车间隔间布局算法研究

半导体制造业是现代工业的重要组成部分，也是一个资金高度密集、生产流程相当复
杂的行业。其中芯片的封装和测试是半导体制造业一个非常重要的环节，其车间一般采取隔间式布局（Bay Layout），在这种布局中，车间被分为很多隔间来放置工艺设备，同一隔间放置相同的设备，并设立WIP 存放区，对于某一隔间而言，如何放置这些相同的设备以及设置WIP 存放区，使得整个隔间的物料搬运成本最小且面积利用率最大成了隔间布局的优化目标，本文针对隔间布局这一目标，并结合半导体封装测试车间整体布局，建立了隔间布局优化数学模型，并提出一种新的优化算法进行解决。
关键词：间式布局；物料搬运成本；面积利用率；优化数学模型
Abstract：Semiconductor manufacturing industry which is highly capital-intensive and complex manufacturing process is an important component of modern industry, and, assembly and test of chips are the very important processes of semiconductor manufacturing. In assembly and test department, the facility layout is Bay-Layout in which the department is formed of bays and same machines are located in one bay and WIP area is also located. So, for one bay, how to allocate the machines and WIP area to minimize the material handing cost and maximize the utilized rate of area are the optimal object of Bay-Layout, and in this paper, the optimal mathematic model of Bay-Layout is established and a new solving algorithm for this mathematic model is proposed.
Key words：Bay-Layout, material handing cost, utilized rate of area, optimal mathematic model