通过设置TriCore的寄存器产生定时中断信号的指令使用介绍

The Infineon TriCore provides an Interrupt System on a high safety standard. This
document contains instructions on how to configure the TriCore registers to generate a timer interrupt based on an overflow trigger from a 32-bit count register.
1 Overview3
2 The basic steps to an Interrupt 4
2.1 The general settings 4
2.2 Service request specific Individual settings4
2.3 Enabling the GPTU by setting the Clock Register CLC 6
2.4 Initialization of the Timer Registers 6
2.5 Software example: Timer Interrupt 9
3 Appendix 12
3.1 xxSRC – Source xx Service Request Control Register..12
3.2 ICR – Interrupt Control Register...13
3.3 T012RUN – Timer Run Control Register..14
3.4 T01IRS – Input and Reload Source Selection Register 16
3.5 T0DCBA – Timer T0 Count Register..17
3.6 T0RDCBA – Timer T0 Reload Register ...17
3.7 T01OTS – Output, Trigger and Service Request Selection Register 18
3.8 GTSRSEL – GPT Service Request Source Selection Register ..19
3.9 CLC – Clock Control Register 20