82C52通用异步收发机的功能及其编程方法

INTRODUCTION  7-4
1.0 GLOSSARY OF DATA COMMUNICATION TERMS  7-4
1.1 Clear to Send  . . . . . . . . . . . . 7-4
1.2 Data Set Ready  . . . . . . . . . . 7-4
1.3 Data Terminal Ready  . . . . . . 7-4
1.4 Framing Error  . . . . . . . . . . . . 7-4
1.5 Interrupt Driven I/O  . . . . . . . . 7-4
1.6 I/O Polling  . . . . . . . . . . . . . . . 7-4
1.7 Overrun Error  . . . . . . . . . . . . 7-5
1.8 Parity  . . . . . . . . . . . . . . . . . . 7-5
1.9 Parity Error  . . . . . . . . . . . . . . 7-5
1.10 Percentage Error in Baud Rate Generation. 7-5
1.11 Request to Send  . . . . . . . . . . 7-6
2.0 CONTROL REGISTERS  . . . . 7-6
2.1 UART Control Register  . . . . . 7-6
2.2 Baud Rate Select Register  . . 7-7
2.3 Modem Control Register  . . . . 7-8
3.0 STATUS REGISTERS . . . . . . 7-10
3.1 UART Status Register . . . . . . 7-10
3.2 Modem Status Register  . . . . 7-11
4.0 TRANSMIT/RECEIVE BUFFER REGISTERS  7-11
4.1 Receiver Buffer Register  . . . . 7-11
4.2 Transmitter Buffer Register  . . 7-12
5.0 I/O MAPPED ADDRESSING . 7-12
5.1 I/O Mapped Addressing  . . . . 7-12
5.2 Memory Mapped I/O  . . . . . . . 7-13
5.3 I/O Addressing for the 82C52  7-13
6.0 RESET OF THE 82C52 . . . . . 7-13
7.0 PROGRAMMING THE 82C52  7-14