IDT_70V05_DST_20120627英文资料

　　Features ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location ◆ High-speed access – Commercial： 15/20/25/35/55ns （max.） – Industrial： 20ns （max.） ◆ Low-power operation – IDT70V05S Active： 400mW （typ.） Standby： 3.3mW （typ.） – IDT70V05L Active： 380mW （typ.） Standby： 660µW （typ.） ◆ IDT70V05 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more thanone device ◆ M/S = VIH for BUSY output flag on Master M/S = VIL for BUSY input on Slave ◆ Interrupt Flag ◆ On-chip port arbitration logic ◆ Full on-chip hardware support of semaphore signaling between ports ◆ Fully asynchronous operation from either port ◆ TTL-compatible， single 3.3V （±0.3V） power supply ◆ Available in 68-pin PGA and PLCC， and a 64-pin TQFP ◆ Industrial temperature range （-40°C to +85°C） is available for selected speeds ◆ Green parts available， see ordering information