Reference System: Ethernet PHY Register Access With GPIO

The XPS Ethernetlite peripheral does not provide any mechanism to access the Ethernet PHY
registers. These registers are used to configure auto negotiation parameters and to obtain PHY status. This application note provides reference systems and associated software to access PHY registers by connecting the serial management bus signals MDC and MDIO to GPIOs which the software controls directly.

The modern Ethernet PHY is highly configurable. The devices used on the Xilinx boards
pertinent to this application note are capable of 10MB, 100MB, or 1000MB operation at full
duplex and half duplex. A PHY will, by default, auto negotiate to the highest possible link speed
it has in common with the peer Ethernet PHY to which it is connected. This behavior is modified
by accessing the appropriate PHY configuration registers.
Many Ethernet MACs will provide a mechanism for the software to access the registers of the
PHY to which it is connected. Because the goal of the XPS Ethernetlite core is to provide a
small, simple Ethernet controller, it does not provide access to the PHY registers. Furthermore,
this MAC is capable of 10/100MB link speeds, not 1000MB. When XPS Ethernetlite is coupled
to a gigabit PHY which is cabled to a PC with a gigabit NIC the auto negotiation defaults will
select a link speed of 1000MB, a speed with which Ethernetlite is not compatible. For proper
operation it is best to configure the PHY so that is will negotiate only 100MB links.
This application note provides a reference system where the PHY serial management interface
signals (MDC, MDIO) are connected to an XPS GPIO peripheral. The PHY registers are
accessed by the software directly manipulating this serial bus clock (MDC) and bidirectional
data (MDIO). Software is provided to configure the onboard PHY so that it will not auto
negotiate to 1000MB.