FB2031 pdf datasheet

FB2031 9-bit latched/registered/pass-thru Futurebus+ transceiver

The FB2031 is a 9-bit latched/registered
transceiver featuring a latched, registered or
pass-thru mode in either the A-to-B or B-to-A
direction. The FB2031 is intended to provide
the electrical interface to a high performance
wired-OR bus.
The TTL-level side (A port) has a common
I/O. The common I/O, open collector B port
operates at BTL signal levels. The logic
element for data flow in each direction is
controlled by two mode select inputs (SEL0
and SEL1). A “00” configures latches in both
directions. A “10” configures thru mode in
both directions. A “01” configures register
mode in both directions. A “11” configures
register mode in the A-to-B direction and
latch mode in the B-to-A direction.
When configured in the buffer mode, the
inverse of the input data appears at the
output port. In the register mode, data is
stored on the rising edge of the appropriate
clock input (LCAB or LCBA). In the latch
mode, clock pins serve as transparent-Low
latch enables. Regardless of the mode, data
is inverted from input to output.
The 3-State A port is enabled by asserting a
High level on OEA. The B port has two output
enables, OEB0 and OEB1. Only when OEB0
is High and OEB1 is Low is the output
enabled.