PEX8615 pdf datasheet

The ExpressLane™ PEX 8615 offers 12 PCI Express Gen 2 (5.0 GT/s) lanes, capable of configuring up to 12 flexible ports and fully conforms to the PCI Express Base Specification, rev 2.0. PEX 8615 architecture supports a high-performance DMA engine with four DMA channels and internal buffer space for internal descriptor support. Up to 256 descriptors are supported internally or alternatively descriptors can also exist in host memory. Each descriptor provides support for large transfer sizes (up to 128MB) giving the user the capability to perform very large data transfers in any direction (memory to device, device to device, memory to memory). PEX 8615 also supports cut-thru with the industry's lowest latency of 140ns (x4 to x1) and offers two virtual channels for traffic prioritization in the system. The device also features an on-chip Non-Transparent port for dual-host and failover applications and supports dual-clock domain operation by virtue of support for Spread Spectrum Clock (SSC) isolation, is offered in a 19 x 19mm 324-ball PBGA and is available in both leaded and lead-free packaging.