AT24C512 pdf datasheet

Features
• Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 3.6V)
• Internally Organized 65,536 x 8
• Two-wire Serial Interface
• Schmitt Triggers, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility
• Write Protect Pin for Hardware and Software Data Protection
• 128-byte Page Write Mode (Partial Page Writes Allowed)
• Self-timed Write Cycle (5 ms Max)
• High Reliability
– Endurance: 100,000 Write Cycles
– Data Retention: 40 Years
• Automotive Devices Available
• 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP,
8-lead LAP, 8-lead SAP and 8-ball dBGA2 Packages
• Die Sales: Wafer Form, Waffle Pack and Bumped Die
Description
The AT24C512 provides 524,288 bits of serial electrically erasable and programmable
read only memory (EEPROM) organized as 65,536 words of 8 bits each. The device’s
cascadable feature allows up to four devices to share a common two-wire bus. The
device is optimized for use in many industrial and commercial applications where lowpower
and low-voltage operation are essential. The devices are available in spacesaving
8-pin PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead
Leadless Array (LAP), and 8-lead SAP packages. In addition, the entire family is available
in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.