74HC139 pdf datasheet

MM54HC139/MM74HC139
Dual 2-To-4 Line Decoder
General Description
This decoder utilizes advanced silicon-gate CMOS technology,
and is well suited to memory address decoding or data
routing applications. It possesses the high noise immunity
and low power consumption usually associated with CMOS
circuitry, yet has speeds comparable to low power Schottky
TTL logic.
The MM54HC139/MM74HC139 contain two independent
one-of-four decoders each with a single active low enable
input (G1, or G2). Data on the select inputs (A1, and B1 or
A2, and B2) cause one of the four normally high outputs to
go low.
The decoder's outputs can drive 10 low power Schottky TTL
equivalent loads, and are functionally as well as pin equivalent
to the 54LS139/74LS139. All inputs are protected from
damage due to static discharge by diodes to VCC and
ground.
Features
Y Typical propagation delays Ð
Select to outputs (4 delays): 18 ns
Select to output (5 delays): 28 ns
Enable to output: 20 ns
Y Low power: 40 mW quiescent supply power
Y Fanout of 10 LS-TTL devices
Y Input current maximum 1 mA, typical 10 pA