通讯设计师在高速背板面临的新挑战

通讯设计师在高速背板面临的新挑战,High-Speed Backplanes Pose New Challenges to Comms Designers
As backplane speeds move beyond 3 Gbit/s, designers will encounter problems not seen at lower rates. Fortunately, through the use of modeling techniques, designers can tackle these issues head on.
The operating data rates of current state-of-the-art backplane serial links are in the 2.5- to 3.125-Gbit/s range. As silicon becomes available that can support higher data rates into the 5- and 10-Gbit/s range, comm system designers are looking for ways to support these higher rates within their existing backplanes.
In the 5- to 10-Gbit/s range, the technical challenges created by phenomenon such as reflections and crosstalk increase. In addition, new voltage- and timing-related challenges have arisen that typically do not exist in lower data rate ranges. These include skin effect, dielectric loss, inter-symbol interference (ISI), and via stub effect.
To overcome these challenges, system designers must develop accurate and efficient models for both the active and the passive components of the system. Silicon vendors also need channel models to successfully design proper on-chip circuits for implementing various techniques like equalization and reflection cancellation. By modeling the known deterministic effects of the channel, signal-integrity related problems can be understood, and techniques can be developed to minimize their impacts.
To develop a backplane model, individual models for connectors, packages, PCB traces and vias are needed. In this article, we'll examine the technical challenges that must be overcome to support 5- to 10-Gbit/s rates, and the corresponding channel model requirements.
Channel Impairments
As the data transfer rate on the channel increases, "old" problems are exacerbated, and "new" problems arise that must be addressed. Figure 1 shows the key timing and voltage related impairments that must be addressed as data rates increase.