片上ESD保护电路

The author first got in touch with the ESD things in late 1996 when he
was a Staff R&D Engineer at the National Semiconductor Corporation,
where he was assigned by the boss to develop some on-chip ESD protection
circuits for mixed-signal IC chips. Ever since then, the not-so-attractive ESD
protection circuit design topics have been on and off the author’s table both
at the company’s cubicle and in the office at the Illinois Institute of
Technology, where the author joined its faculty team of Electrical and
Computer Engineering in Fall 1998. Exactly like all the other IC designers,
the author does not really like the little ESD thing and has no fun in doing
ESD protection circuit design. Unfortunately, life is life. One has to deal
with some unpleasant issues sometime somewhere somehow. The harsh
reality is that an IC designer must find the right ESD protection solution for
the IC chips. If there is no ESD protection provided, nobody will buy your
chips. If there is no sufficient ESD protection for your chips, you will lose
the market to your competitors. Period! What makes an IC designer’s life
even more miserable is the fact that as IC technologies advance, the
customer demands for IC ESD robustness and the complexity of on-chip
ESD protection circuit design increase dramatically, as evidenced by the
huge amount of related papers published in the past decade. While
significant progresses have been made in the field of ESD protection
research and design, IC designers are deeply bothered by the situation that
there are too much qualitative sayings and too few quantitative analyses on
the ESD protection design matters. Hence, very little success in predicting
ESD protection circuit design is expected. One question commonly heard in
the IC circuit design community is that “how do I design the ESD protection
for my chips, with prediction, as a circuit designer?” This book tries to
provide the information necessary to address this tough design challenge
from an IC circuit designer’s angle.