产品信息
描述The TLV1562 is a 10-bit CMOS low-power, high-speed programmable resolution analog-to-digital converter based on a low-power recyclic architecture. The unique architecture delivers a throughput up to 2 MSPS (million samples per second) at 10-bit resolution. The programmable resolution allows a higher conversion throughput as a tradeoff of lower resolution. A high speed 3-state parallel port directly interfaces to a digital signal processor (DSP) or microprocessor (uP) system data bus. D0 through D9 are the digital output terminals with D0 being the least significant bit (LSB). The TLV1562 is designed to operate for a wide range of supply voltages (2.7 V to 5.5 V) with very low power consumption (11 mA maximum at 5.5 V, 10 MHz CLKIN). The power saving feature is further enhanced with a software power-down feature (1 uA maximum) and auto power-down (1 uA maximum) feature. Many programmable features make this device a flexible general-purpose data converter. The device can be configured as either four single-ended inputs to maximize the capacity or two differential inputs to improve noise immunity. The internal system clock (SYSCLK) may come from either an internally generated OSC or an external clock source (CLKIN). Four different modes of conversion are available for different applications. The interrupt driven modes are mostly suitable for asynchronous applications, while the continuous modes take advantage of the high speed nature of a pipelined architecture. A pair of built-in sample-and-hold amplifiers allow simultaneous sampling of two input channels. This makes the TLV1562 perfect for communication applications. Conversion is started by the RD\ signal, which can also be used for reading data, to maximize the throughput. Conversion can be started either by the RD\ or CSTART\ signal when the device is operating in the interrupt-driven modes. The dedicated conversion start pin, CSTART\, provides a mechanism to simultaneously sample and convert multiple channels when multiple converters are used in an application. The converter incorporates a pair of differential high-impedance reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry from logic and supply noise. Other features such as low input capacitance (10 pF) and very wide input bandwidth (75 MHz) make this device a perfect digital signal processing (DSP) companion for mobile communication applications. A switched-capacitor design allows low-error conversion over the full operating free-air temperature range. The features that make this device truly a DSP friendly converter include: 1) programmable continuous conversion modes, 2) programmable 2s complement output code format, and 3) programmable resolution. The TLV1562 is offered in both 28-pin TSSOP and SOIC packages. The TLV1562C is characterized for operation from 0°C to 70°C. The TLV1562I is characterized for operation over the full industrial temperature range of -40°C to 85°C.特性2 MSPS Max Throughput at 10 Bit (Single Channel), ±1 LSB DNL, ±1 LSB INL MAX 3 MSPS Max Throughput at 8 Bit (Single Channel), ±1 LSB DNL, ±1 LSB INL MAX 7 MSPS Max Throughput at 4 Bit (Single Channel), ±0.4 LSB DNL, ±0.4 LSB INL MAX No Missing Code for External Clock Up to 15 MHz at 5.5 V, 12 MHz at 2.7 V ENOB 9.4 Bit, SINAD 57.8 dB, SFDR -70.8 dB, THD -68.8 dB, at fi = 800 kHz, 10 Bit Wide Input Bandwidth for Undersampling (75 MHz at 1 dB, >120 MHz at -3 dB) at Rs = 1 kSoftware Programmable Power Down, (1 uA), Auto Powerdown (120 uA) Single Wide Range Supply 2.7 VDC to 5.5 VDC Low Supply Current 11 mA at 5.5 V, 10 MHz; 7 mA at 2.7 V, 8 MHz Operating Simultaneous Sample and Hold: Dual Sample and Hold Matched Channels Multi Chip Simultaneous Sample and Hold Capable Programmable Conversion Modes: Interrupt-Driven for Shorter Latency Continuous Modes Optimized for MIPS Sensitive DSP Solutions Built-In Internal/System Mid-Scale Error Calibration Built-In Mux With 2 Differential or 4 Single-Ended Input Channels Low Input Capacitance (10 pF Max Fixed, 1 pF Max Switching) DSP/u P-Compatible Parallel Interface
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