TMS320C6743 定点/浮点数字信号处理器

数据： TMS320C6743 Fixed- and Floating-Point Digital Signal Processor 数据表

描述

C6743器件是一款基于C674x DSP内核的低功耗数字信号处理器。与TMS320C6000™DSP平台的其他成员相比，该器件的功耗显着降低。

C6743器件使原始设备制造商（OEM）和原始设计制造商（ODM）能够快速推向市场高处理性能。

C6743 DSP内核采用基于缓存的两级架构。 1级程序高速缓存（L1P）是32 KB直接映射高速缓存，1级数据高速缓存（L1D）是32 KB双向组关联高速缓存。 Level 2程序缓存（L2P）由128 KB的内存空间组成，在程序和数据空间之间共享。 L2内存可以配置为映射内存，缓存或两者的组合。

外设集包括：带管理数据输入/输出（MDIO）模块的10/100 Mbps以太网MAC（EMAC）;两个I ² C总线接口;两个带有14/9串行器和FIFO缓冲器的多通道音频串行端口（McASP）;两个64位通用定时器，每个都可配置（一个可配置为看门狗）;多达8个16引脚的通用输入/输出（GPIO），具有可编程中断/事件生成模式，与其他外设复用;两个UART接口（一个具有 RTS 和 CTS ）;三个增强型高分辨率脉冲宽度调制器（eHRPWM）外设;三个32位增强型捕获（eCAP）模块外设，可配置为3个捕获输入或3个辅助脉冲宽度调制器（APWM）输出;两个32位增强型正交编码脉冲（eQEP）外设;和2个外部存储器接口（EMIF）：用于较慢存储器或外设的异步外部存储器接口（EMIFA），以及用于SDRAM的高速存储器接口（EMIFB）。

以太网媒体访问控制器（EMAC）提供C6743和网络之间的有效接口。 EMAC支持10Base-T和100Base-TX，或半双工或全双工模式下的10 Mbps和100 Mbps。此外，MDIO接口可用于PHY配置。

丰富的外设集可以控制外部外围设备并与外部处理器通信。有关每个外围设备的详细信息，请参阅本文档后面的相关章节以及相关的外围设备参考指南。

特性

Applications
- Networking
- High-Speed Encoding
- Professional Audio™
Software Support
- TI DSP/BIOS™
- Chip Support Library and DSP Library
375-MHz TMS320C674x Fixed- and Floating-Point VLIW DSP Core
- Load-Store Architecture with Nonaligned Support
- 64 General-Purpose Registers (32-Bit)
- Six ALU (32- and 40-Bit) Functional Units
  - Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
  - Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks
  - Supports up to Two Floating Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
- Two Multiply Functional Units
  - Mixed-Precision IEEE Floating Point Multiply Supported up to:
    - 2 SP x SP -> SP Per Clock
    - 2 SP x SP -> DP Every Two Clocks
    - 2 SP x DP -> DP Every Three Clocks
    - 2 DP x DP -> DP Every Four Clocks
  - Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Hardware Support for Modulo Loop
  Operation
- Protected Mode Operation
- Exceptions Support for Error Detection and Program Redirection
C674x Instruction Set Features
- Superset of the C67x+ and C64x+ ISAs
- 3000 MIPS and 2250 MFLOPS C674x
- Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- Compact 16-Bit Instructions
C674x Two-Level Cache Memory Architecture
- 32KB of L1P Program RAM/Cache
- 32KB of L1D Data RAM/Cache
- 128KB of L2 Unified Mapped RAM/Cache
- Flexible RAM/Cache Partition (L1 and L2)
Enhanced Direct Memory Access Controller 3 (EDMA3):
- 2 Transfer Controllers
- 32 Independent DMA Channels
- 8 Quick DMA Channels
- Programmable Transfer Burst Size
3.3-V LVCMOS I/Os
Two External Memory Interfaces:
- EMIFA
  - NOR (8-Bit-Wide Data)
  - NAND (8-Bit-Wide Data)
- EMIFB
  - 16-bit SDRAM, up to 128MB
Two Configurable 16550-Type UART Modules:
- UART0 with Modem Control Signals
- 16-Byte FIFO
- 16x or 13x Oversampling Option
One Serial Peripheral Interface (SPI) with One Chip Select
Multimedia Card (MMC)/Secure Digital (SD)
Two Master and Slave Inter-Integrated Circuit (I²C Bus™)
Programmable Real-Time Unit Subsystem (PRUSS)
- Two Independent Programmable Real-Time Unit (PRU) Cores
  - 32-Bit Load-Store RISC Architecture
  - 4KB of Instruction RAM per Core
  - 512 Bytes of Data RAM per Core
  - PRUSS can be Disabled Through Software to Save Power
  - Register 30 of each PRU is Exported from the Subsystem in Addition to the Normal R31 Output of the PRU Cores
- Standard Power-Management Mechanism
  - Clock Gating
  - Entire Subsystem Under a Single PSC Clock Gating Domain
- Dedicated Interrupt Controller
- Dedicated Switched Central Resource
Two Multichannel Audio Serial Ports (McASPs):
- Supports TDM, I2S, and Similar Formats
- FIFO Buffers for Transmit and Receive
10/100 Mbps RMII Ethernet Media Access Controller (EMAC):
- IEEE 802.3 Compliant (3.3-V I/O Only)
- RMII Media-Independent Interface
- Management Data I/O (MDIO) Module
One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit Timers)
Three Enhanced Pulse Width Modulators (eHRPWMs):
- Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
- 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
- Dead-Band Generation
- PWM Chopping by High-Frequency Carrier
- Trip Zone Input
Three 32-Bit Event Capture (eCAP) Modules:
- Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
- Single-Shot Capture of up to Four Event Time-Stamps
Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
176-Pin Thin Quad Flat Pack (TQFP) [PTP Suffix], 0.5-mm Pin Pitch
Commercial or Automotive Temperature

参数与其它产品相比音频处理器


DSP
DSP MHz (Max)
Arm CPU
Operating Systems
DRAM
On-Chip L2 Cache/RAM
Approx. Price (US$)
Operating Temperature Range (C)
McASP
McBSP
USB
EMAC
Package Group
PCI/PCIe
I2C
UART (SCI)
DSP MMACS
Other Hardware Acceleration

TMS320C6743
1 C674x
200 375
N/A
TI RTOS
SDRAM
128 KB
8.55 \| 1ku
-40 to 125 0 to 90
2
0
0
10/100
BGA HLQFP
N/A
2
2
3000
PRU-ICSS

方框图 (1)

技术文档

数据手册（1）

TMS320C6743 Fixed- and Floating-Point Digital Signal Processor 数据表

元器件购买 TMS320C6743 相关库存

搜索历史

TMS320C6743 定点/浮点数字信号处理器

描述

特性

参数与其它产品相比音频处理器

方框图 (1)

技术文档

相关阅读

处理器相关文章

处理器相关下载

音频处理器相关文章

音频处理器相关下载

数字信号处理器相关文章

数字信号处理器相关下载

媒体处理器相关文章

媒体处理器相关下载

搜索历史

TMS320C6743 定点/浮点数字信号处理器

描述

特性

参数 与其它产品相比 音频处理器

方框图 (1)

技术文档

相关阅读

处理器相关文章

处理器相关下载

音频处理器相关文章

音频处理器相关下载

数字信号处理器相关文章

数字信号处理器相关下载

媒体处理器相关文章

媒体处理器相关下载

参数与其它产品相比音频处理器