DRA750 适用于信息娱乐应用的双 1.0GHz A15、双 DSP、扩展外设 SoC 处理器

数据： DRA75x, DRA74x Infotainment Applications Processor Silicon Revision 2.0 数据表

描述

DRA75x和DRA74x（Jacinto 6）信息娱乐应用处理器旨在满足现代信息娱乐系统汽车体验的强烈处理需求。

<该设备使原始设备制造商（OEM）和原始设计制造商（ODM）能够快速实施创新的连接技术，语音识别，音频流等。 Jacinto 6器件通过完全集成的混合处理器解决方案的最大灵活性带来高处理性能。这些器件还将可编程视频处理与高度集成的外设集合在一起。

可编程性由双核ARM Cortex-A15 RISC CPU提供，具有Neon™扩展，TI C66x VLIW浮点DSP内核和Vision AccelerationPac（带有一个或多个EVE）。 ARM允许开发人员将控制功能与DSP和协处理器上编程的其他算法分开，从而降低系统软件的复杂性。

此外，TI还为ARM，DSP提供了一整套开发工具。和EVE协处理器，包括C编译器和用于查看源代码的调试接口。

DRA75x和DRA74x Jacinto 6处理器系列符合AEC-Q100标准。

特性

Architecture Designed for Infotainment Applications
Video, Image, and Graphics Processing Support
- Full-HD Video (1920 × 1080p, 60 fps)
- Multiple Video Input and Video Output
- 2D and 3D Graphics
Dual ARM^® Cortex^®-A15 Microprocessor Subsystem
Up to two C66x Floating-Point VLIW DSP
- Fully Object-Code Compatible With C67x and C64x+
- Up to Thirty-two 16 x 16-Bit Fixed-Point Multiplies per Cycle
Up to 2.5MB of On-Chip L3 RAM
Level 3 (L3) and Level 4 (L4) Interconnects
Two DDR2/DDR3/DDR3L Memory Interface (EMIF) Modules
- Supports up to DDR2-800 and DDR3-1066
- Up to 2GB Supported per EMIF
Dual ARM® Cortex®-M4 Image Processing Units (IPU)
Up to Two Embedded Vision Engines (EVEs)
IVA Subsystem
Display Subsystem
- Display Controller With DMA Engine and up to Three Pipelines
- HDMI™ Encoder: HDMI 1.4a and DVI 1.0 Compliant
Video Processing Engine (VPE)
2D-Graphics Accelerator (BB2D) Subsystem
- Vivante^® GC320 Core
Dual-Core PowerVR^® SGX544 3D GPU
Three Video Input Port (VIP) Modules
- Support for up to 10 Multiplexed Input Ports
General-Purpose Memory Controller (GPMC)
Enhanced Direct Memory Access (EDMA) Controller
2-Port Gigabit Ethernet (GMAC)
Sixteen 32-Bit General-Purpose Timers
32-Bit MPU Watchdog Timer
Five Inter-Integrated Circuit (I²C) Ports
HDQ™/1-Wire^® Interface
SATA Interface
Media Local Bus (MLB) Subsystem
Ten Configurable UART/IrDA/CIR Modules
Four Multichannel Serial Peripheral Interfaces (McSPI)
Quad SPI (QSPI)
Eight Multichannel Audio Serial Port (McASP) Modules
SuperSpeed USB 3.0 Dual-Role Device
Three High-Speed USB 2.0 Dual-Role Devices
Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD^®/SDIO)
PCI-Express^® 3.0 Subsystems With Two 5-Gbps Lanes
- One 2-lane Gen2-Compliant Port
- or Two 1-lane Gen2-Compliant Ports
Dual Controller Area Network (DCAN) Modules
- CAN 2.0B Protocol
Up to 247 General-Purpose I/O (GPIO) Pins
Real-Time Clock Subsystem (RTCSS)
Device security features
- Hardware Crypto accelerators and DMA
- Firewalls
- JTAG^® lock
- Secure keys
- Secure ROM and boot
Power, Reset, and Clock Management
On-Chip Debug With CTools Technology
28-nm CMOS Technology
23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA (ABC)

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参数与其它产品相比 DRAx 信息娱乐系统 SOC


Arm CPU
Arm MHz (Max.)
DSP
DSP MHz (Max)
Graphics Acceleration
Co-Processor(s)
Display Options
Hardware Accelerators
EMIF
DRAM
Other On-Chip Memory
EMAC
Video Input Ports
Serial I/O
MMC/SD
PCIe
USB
McASP
Security Enabler

DRA750	DRA756
2 ARM Cortex-A15	2 ARM Cortex-A15
1000	1500
2 C66x	2 C66x
750	750
1 2D 2 3D	1 2D 2 3D
2 Dual ARM Cortex-M4	2 ARM Cortex-M4
1 HDMI OUT 3 LCD OUT	1 HDMI OUT 3 LCD OUT
1 Image Video Accelerator 2 Viterbi Decoder Audio Tracking	2 EVE 1 Image Video Accelerator 2 Viterbi Decoder Audio Tracking
2 32-bit	2 32-bit
DDR2-800 DDR3-1066 DDR3L-1066	DDR2-800 DDR3-1066 DDR3L-1066
512 KB	2.5 MB
10/100/1000 2-port 1Gb switch	10/100/1000 2-port 1Gb switch
10	10
CAN I2C SPI UART USB	CAN I2C SPI UART USB
1x SDIO 4b 1x SDIO 8b 1x UHSI 4b 1x eMMC 8b	1x SDIO 4b 1x SDIO 8b 1x UHSI 4b 1x eMMC 8b
2 PCIe Gen2	2 PCIe Gen2
1 USB3.0 3 USB2.0	1 USB3.0 3 USB2.0
8	8
Cryptographic acceleration Debug security Device identity Secure boot Secure storage Trusted execution environment	Cryptographic acceleration Debug security Device identity Secure boot Secure storage Trusted execution environment
无样片	无样片