66AK2G12 多核 DSP+ARM KeyStone II 片上系统 (SoC)

• Processor Cores:
• ARM^® Cortex^®-A15 Microprocessor Unit (ARM A15) Subsystem at up to 1000 MHz
  • Supports Full Implementation of ARMv7-A Architecture Instruction Set
  • Integrated SIMDv2 (NEON™ Technology) and VFPv4 (Vector Floating Point)
  • 32KB of L1 Program Memory
  • 32KB of L1 Data Memory
  • 512KB of L2 Memory
  • Error Correction Code (ECC) Protection for L1 Data Memory ECC for L2 Memory
  • Parity Protection for L1 Program Memory
  • Global Timebase Counter (GTC)
    • 64-Bit Free-Running Counter That Provides Timebase for ARM A15 InternalTimers
    • Compliant to ARM V7 MPCore Architecture for Generic Timers
• C66x Fixed- and Floating-Point VLIW DSP Subsystem at up to 1000 MHz
  • Fully Object-Code Compatible With C67x+ and C64x+ Cores
  • 32KB of L1 Program Memory
  • 32KB of L1 Data Memory
  • 1024KB of L2 Configurable as L2 RAM or Cache
  • Error Detection for L1 Program Memory
  • ECC for L1 Data Memory
  • ECC for L2 Data Memory
• Industrial Subsystem:
• Up to Two Programmable Real-Time Unit and Industrial Communication Subsystems (PRU-ICSS), Each Supports:
  • Two Programmable Real-Time Units (PRUs) With Enhanced Multiplier and Accumulator, Each PRU Supports:
    • 16KB of Program Memory WithECC
    • 8KB of Data Memory With ECC
    • CRC32 and CRC16 HardwareAccelerator
    • 20 × Enhanced GPIO
    • Serial Capture Unit (SCU),Supporting Direct Connection, 16-bit Parallel Capture, 28-bit Shift, MII_RT, EnDat 2.2 Protocol andSigma-Delta Demodulation
    • Scratch Pad and XFR DirectConnect
  • 64KB of General-Purpose Memory With ECC
  • One Ethernet MII_RT Module with Two MII Ports Configurable for Connection With Each PRU; Support Multiple Industrial Communication Protocols
  • Industrial Ethernet Peripheral (IEP) to Manage and Generate Industrial Ethernet Functions
  • Built-In Universal Asynchronous Receiver and Transmitter (UART) 16550, With a Dedicated 192-MHz Clock to Support 12-Mbps PROFIBUS^®
  • Built-In Industrial Ethernet 64-Bit Timer
  • Built-In Enhanced Capture Module (eCAP)
• Memory Subsystem:
• Multicore Shared Memory Controller (MSMC) With 1024KB of Shared L2 RAM
  • Provides High-Performance Interconnect to Internal Shared SRAM and DDR EMIF for Both ARM A15 and C66x Access
  • Supports ARM I/O Coherency Where ARM A15 is Cache Coherent to Other System Masters Accessing the MSMC-SRAM or DDR EMIF
  • Supports ECC on SRAM
• Up to 36-Bit DDR External Memory Interface (EMIF)
  • Supports DDR3L at up to 1066 MT/s
  • Supports 4-GB Memory Address Range
  • Supports 32-Bit SDRAM Data Bus With 4-bit ECC
  • Supports 16-Bit and 32-Bit SDRAM Data Bus Without ECC
• General-Purpose Memory Controller (GPMC)
  • Flexible 8- and 16-Bit Asynchronous Memory Interface With up to Four Chip Selects
  • Supports NOR, Muxed-NOR, SRAM
  • Supports General-Purpose Memory-Port Expansion With the Following Modes:
    • Asynchronous Read and Write Access
    • Asynchronous ReadPage Access (4-, 8-, 16-Word16)
    • Synchronous Read and WriteAccess
    • Synchronous Read Burst Access Without Wrap Capability (4-, 8-,16-Word16)
• Network Subsystem (NSS):
• Ethernet MAC Subsystem (EMAC)
  • One-Port Gigabit Ethernet: RMII, MII, RGMII
  • Supports 10-, 100-, 1000-Mbps Full Duplex
  • Supports 10-, 100-Mbps Half Duplex
  • Supports Ethernet Audio Video Bridging (eAVB)
  • Maximum Frame Size 2016 Bytes (2020 Bytes With VLAN)
  • Eight Priority Level QOS Support (802.1p)
  • IEEE 1588v2 (2008 Annex D, Annex E, and
    Annex F) to Facilitate Audio Video Bridging 802.1AS Precision Time Protocol
  • CPTS Module With Timestamping Support for IEEE 1588v2
  • DSCP Priority Mapping (IPv4 and IPv6)
  • MDIO Module for PHY Management
  • Enhanced Statistics Collection
• Navigator Subsystem (NAVSS)
  • Built-In Packet DMA Controller for Optimized Network Processing
  • Built-In Queue Manager (QM) for Optimized Network Processing
    • Supports up to 128 Queues
    • 2048 Buffers Supported inInternal Queue RAM
• Crypto Engine (SA) Supports:
  • Crypto Function Library for AES, DES, 3DES, SHA1, MD5, SHA2-224 and SHA2-256 Operations
  • Block Data Encryption Supported Through Hardware Cores
    • AES With 128-, 192-, and 256-Bit Key Supports
    • DESand 3DES With 1, 2, or 3 Different Key Support
  • Programmable Mode Control Engine (MCE)
  • Public Key Accelerator (PKA) With Elliptic Curve Cryptography
  • Elliptic Curve Diffie–Hellman (ECDH) Based Key Exchange and Digital Signature (ECDSA) Applications
  • Authentication for SHA1, MD5, SHA2-224 and SHA2-256
  • Keyed HMAC Operation Through Hardware Core
  • True Random Number Generator (TRNG)
• Display Subsystem:
• Supports One Video Pipe With In-Loop Scaling, Color Space
• Conversion and Background Color Overlay
• Input Data Format: BITMAP, RGB16, RGB24, RGB32, ARGB16, ARGB32, YUV420, YUV422, and RGB565-A8
• Supported Display Interfaces:
  • MIPI^® DPI 2.0 Parallel Interface
  • RFBI (MIPI-DBI 2.0) up to QVGA at 30fps
  • BT.656 4:2:2
  • BT.1120 4:2:2 up to 1920 × 1080 at 30fps
• In-Loop Scaling Capability
• LCD Display Interface Supports:
  • Active Matrix (TFT)
  • Passive Matrix (STN)
  • Grayscale
  • TDM
  • AC Bias Control
  • Dither
  • CPR
• Asynchronous Audio Sample Rate Converter (ASRC)
• High performance Asynchronous Sample Rate Converter with 140dB Signal-to-Noise (SNR)
• Up to 8 Stereo Streams (16 Audio Channels)
• Automatically Sensing / Detection of Input Sample Frequencies
• Attenuation of Sampling Clock Jitter
• 16-, 18-, 20-, 24-Bit Data Input/Output
• Audio Sample Rates from 8 kHz to 216 kHz
• Input/Output Sampling Ratios from 16:1 to 1:16
• Group Mode, Where Multiple ASRC Blocks Use the Same Timing Loop for Input or Output
• Linear Phase FIR Filter
• Controllable Soft Mute
• Independent Clock Generator, and Rate and Stamp Generator, for Each Input and Output Clock Zone
• Separate DMA Events for Input and Output, for Each Channel and Group
• High-Speed Serial Interfaces:
• PCI Express^® 2.0 Port with Integrated PHY:
  • Single Lane Gen2-Compliant Port
  • Root Complex (RC) and End Point (EP) Modes
• Up to Two USB 2.0 High-Speed Dual-Role Ports With Integrated PHYs, Support:
  • Dual-role-device (DRD) Capability With:
    • USB 2.0 Peripheral (or Device) at
      HS (480Mbps) and FS (12Mbps) Speeds
    • USB 2.0 Host at HS(480Mbps),
      FS (12Mbps), and LS (1.5Mbps) Speeds
    • USB 2.0 Static Peripheral and Static HostOperations
  • xHCI Controller With the Following Features:
    • Compatible to the xHCI Specification (revision 1.1) in Host Mode
    • All Modes of Transfer (Control, Bulk, Interrupt, andIsochronous)
    • 15 Transmit (TX), 15 Receive (RX) Endpoints (EPs), and OneBidirectional EP0 Endpoint
• Flash Media Interfaces:
• QSPI™ With XIP and up to Four Chip Selects, Supports:
  • Memory-Mapped Direct Mode of Operation for Performing FLASH Data Transfers and Executing Code From FLASH Memory (XIP)
  • Supports up to 96 MHz
  • Internal SRAM Buffer With ECC
  • High Speed Read Data Capture Mechanism
• Two Multimedia Card (MMC) and Secure Digital (SD) Ports
  • Supports JEDEC JESD84 v4.5-A441 and SD3.0 Physical Layer With SDA3.00 Standards
  • MMC0 Supports 3.3-V I/O for:
    • SD DS and HS Mode
    • eMMC Mode HS-SDR and DDR
      up to 48 MHz
  • MMC1 Supports 1.8-V I/O Modes for eMMC, Including HS-SDR and DDR at up to 48 MHz With 4- and 8-Bit Bus Width
• Audio Peripherals:
• Three Multichannel Audio Serial Port (McASP) Peripherals
  • Transmit and Receive Clocks up to 50 MHz
  • Two Independent Clock Zones and Independent Transmit and Receive Clocks per McASP
  • Up to 16-, 10-, 6-Serial Data Pins for McASP0, McASP1, and McASP2, Respectively
  • Supports TDM, I2S, and Similar Formats
  • Supports DIT Mode
  • Built-In FIFO Buffers for Optimized System Traffic
• Multichannel Buffered Serial Port (McBSP)
  • Transmit and Receive Clocks up to 50 MHz
  • Two Clock Zones and Two Serial-Data Pins
  • Supports TDM, I2S, and Similar Formats
• Automotive Peripherals:
• Two Controller Area Network (CAN) Ports
  • Supports CAN v2.0 Part A, B (ISO 11898-1) Protocol
  • Bit Rates up to 1 Mbps
  • Dual Clock Source
  • ECC Protection for Message RAM
• One Media Local Bus (MLB)
  • Supports Both 3-Pin (Up to MOST50, 1024 × Fs) and 6-Pin (Up to MOST150, 2048 × Fs) Versions of MediaLB^® Physical Layer Specification v4.2
  • Supports All Types of Data Transfer Over 64 Logical Channels (Synchronous Stream, Isochronous, Asynchronous Packet, Control Message)
  • Supports 3-Wire MOST 150 Protocol
• Real-Time Control Interfaces:
• Six Enhanced High Resolution Pulse Width Modulation (eHRPWM) Modules, Each Counter Supports:
  • Dedicated 16-Bit Time-Base With Period and Frequency Control
  • Two Independent PWM Outputs With Single Edge Operation
  • Two Independent PWM Outputs With Dual-Edge Symmetric Operation
  • One Independent PWM Output With Dual-Edge Asymmetric Operation
• Two 32-Bit Enhanced Capture Modules (eCAP):
  • Supports One Capture Input or One Auxiliary PWM Output Configuration Options
  • 4-Event Time-Stamp Registers (Each 32-Bits)
  • Interrupt on Either of the Four Events
• Three 32-Bit Enhanced Quadrature Pulse Encoder Modules (eQEP), Each Supports:
  • Quadrature Decoding
  • Position Counter and Control Unit for Position Measurement
  • Unit Time Base for Speed and Frequency Measurement
• General Connectivity:
• Three Inter-Integrated Circuit (I²C) Interfaces, Each Supports:
  • Standard (up to 100 kHz) and
    Fast (up to 400 kHz) Modes
  • 7-Bit Addressing Mode
  • Supports EEPROM Size Up to 4Mbit
• Four Serial Peripheral Interfaces (SPI), Each Supports:
  • Operates at up to 50 MHz in Master Mode and 25 MHz in Slave Mode
  • Two Chip Selects
• Three UART Interfaces
  • All UARTs are 16C750-Compatible and Operate at Up to 3M Baud
  • UART0 Supports 8 Pins With Full Modem Control, With DSR, DTR, DCD, and RI Signals
  • UART1 and UART2 are 4-Pin Interfaces
• General-Purpose I/O (GPIO)
  • Up to 212 GPIOs Muxed With Other Interfaces
  • Can be Configured as Interrupt Pins
• Timers and Miscellaneous Modules:
• Seven 64-Bit Timers:
  • Two 64-Bit Timers Dedicated to ARM A15 and DSP Cores (One Timer per Core)
    • Watchdog and General-Purpose (GP)
  • Four 64-Bit Timers are Shared for General Purposes
  • Each 64-Bit Timer Can be Configured as Two Individual 32-Bit Timers
  • One 64-Bit Timer Dedicated for PMMC
  • Two Timers Input/Output Pin Pairs
• Interprocessor Communication With:
  • Message Manager to Facilitate Multiprocessor Access to the PMMC:
    • Provides Hardware Acceleration for Pushing and Popping Messages to/fromLogical Queues
    • Supports Up to 64 Queues and 128 Messages
  • Semaphore Module With Up to 64 Independent Semaphores and 16 Masters (device cores)
• EDMA With 128 (2 × 64) Channels and
  1024 (2 × 512) PaRAM Entries
• Keystone II System on Chip (SoC) Architecture:
• Security
  • Supports General-Purpose (GP) and High-Secure (HS) Devices
  • Supports Secure Boot
  • Supports Customer Secondary Keys
  • 4KB of One-Time Programmable (OTP) ROM for Customer Keys
• Power Management
  • Integrated Power Management Microcontroller (PMMC) Technology
• Supports Primary Boot From UART, I²C, SPI, GPMC, SD or eMMC, USB Device Firmware Upgrade v1.1, PCIe^®, and Ethernet Interfaces
• Keystone II Debug Architecture With Integrated ARM CoreSight™ Support and Trace Capability
• Operating Temperature (T_J):
• –40°C to 125°C (Automotive)
• –40°C to 105°C (Extended)
• 0°C to 90°C (Commercial)

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