双通道 370MSPS 接收器和反馈 IC
| Number of input channels | 2 |
| Resolution (Bits) | 14 |
| Sample rate (Max) (MSPS) | 370 |
| Features | Decimating Filter, Differential Inputs, High Dynamic Range, Nap Mode, Out of Range Indicator, Power Down |
| Analog input BW (MHz) | 800 |
| SFDR (Typ) (dB) | 88 |
| SNR (Typ) (dB) | 71.9 |
| Power consumption (Typ) (mW) | 1752 |
| Logic voltage DV/DD (Max) (V) | 1.25 |
| Logic voltage DV/DD (Min) (V) | 1.15 |
| Analog voltage AVDD (Max) (V) | 3.45 |
| Analog voltage AVDD (Min) (V) | 1.15 |
| Operating temperature range (C) | -40 to 85 |
| Rating | Catalog |
- Conversion Rate: 370 MSPS
- 1.7 VP-P Input Full Scale Range
- SNRBoost Noise Shaping with 100 MHz Bandpass Bandwidth
- Noise Spectral Density: –152.0 dBFS/Hz
- Programmable Passband Center Frequency
- Bit-Burst Resolution Switching
- Resolutions: 9-bit (Low-Res), 14-bit (Hi-Res)
- Hi-Res Noise Density: –152.7 dBFS/Hz
- Programmable Burst Configurations
- Performance
- Input: 150 MHz, –3 dBFS
- SNR (SNRBoost): 71.6 dBFS
- SNR (Bit-Burst): 69.6 dBFS
- SFDR: 88 dBFS
- non-HD2/HD3 SPUR: –90 dBFS
- Input: 150 MHz, –3 dBFS
- Power Dissipation: 876 mW/channel
- Buffered Analog Inputs
- On-chip Precision Reference Without External Bypassing
- Input Sampling Clock Divider with Phase Synchronization
(Divide-by- 1, 2, 4 or 8) - JESD204B Subclass 1 Serial Data Interface
- Lane Rates up to 7.4 Gb/s
- Configurable as 1- or 2-lanes/channel
- Fast Over-range Signals
- 4-wire, 1.2 V, 1.8 V, 2.5V or 3.3V Compatible SPI
- 56-pin QFN Package, (8 × 8 mm, 0.5mm pin-pitch)
The LM97937 device is a dual-channel 370 MSPS analog-to-digital converter (ADC) with JESD204B interface operating up to 7.4 Gb/s. SNRBoost technology with bandpass spectral shaping improves the noise density at the intermediate frequency and Bit-Burst technology provides temporary and periodic resolution enhancement. The integrated input buffer reduces charge kick-back noise and eases the system level design of the driving amplifier, anti-aliasing filter and impedance matching. An input sampling clock divider provides integer divide ratios with configurable phase selection to simplify system clocking. The device comes in a 56-pin, 8-mm × 8-mm QFN package.
