| Function | Serializer |
| Color depth (bpp) | 12 |
| Input compatibility | LVCMOS |
| Pixel clock frequency (Max) (MHz) | 100 |
| Output compatibility | FPD-Link III LVDS |
| Features | Low-EMI Point-to-Point Communication |
| Signal conditioning | Adaptive Equalizer |
| EMI reduction | LVDS |
| Diagnostics | BIST |
| Operating temperature range (C) | -40 to 105 |
- AEC-Q100 qualified for automotive applications with the following results:
- Device temperature grade 2: –40°C to +105°C ambient operating temperature
- 56.25-MHz to 100-MHz input pixel clock support
- Robust Power-Over-Coaxial (PoC) operation
- Programmable data payload:
- 8/10-Bit payload 75-MHz to 100-MHz
- 12-Bit payload 56.25-MHz to 100-MHz
- Continuous low latency bidirectional control interface channel with I2C support at 400-kHz
- Embedded clock with DC-balanced coding to support AC-coupled interconnects
- Capable of driving up to 15-m coaxial or Shielded Twisted-Pair (STP) cables
- 4 Dedicated General-Purpose Input/Output (GPIO)
- 1.8-V, 2.8-V or 3.3-V compatible parallel inputs on serializer
- Single power supply at 1.8-V
- ISO 10605 and IEC 61000-4-2 ESD compliant
- Compatible with DS90UB66x-Q1 and DS90UB63x-Q1 deserializers
The DS90UB633A-Q1 device offers an FPD-Link III interface with a high-speed forward channel and a bidirectional control channel for data transmission over a single coaxial cable or differential pair. The DS90UB633A-Q1 device incorporates differential signaling on both the high-speed forward channel and bidirectional control channel data paths. The serializer/deserializer pair is targeted for connections between imagers and video processors in an electronic control unit (ECU). This device is ideally suited for driving video data requiring up to 12-bit pixel depth plus two synchronization signals along with bidirectional control channel bus.
Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical-bidirectional control channel information. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. Internal DC-balanced encoding/decoding is used to support AC-coupled interconnects.
