| Number of ADC channels | 2 |
| Number of DAC channels (#) | 2 |
| Digital audio interface | L, R, I2S, DSP, TDM |
| Analog inputs | 10 |
| Sampling rate (Max) (kHz) | 96 |
| Rating | Automotive |
| Features | Matrix mixing, Phase-locked loop (PLL), Headset detect, Stereo headphone amplifier |
| ADC SNR (Typ) (dB) | 92 |
| DAC SNR (Typ) (dB) | 102 |
| | |
- Qualified for Automotive Applications
- AEC-Q100 Qualified With the Following Results:
- Device Temperature Grade 3: –40°C to 85°C
Ambient Operating Temperature Range - Device HBM ESD Classification Level 1C
- Device CDM ESD Classification Level C6
- Device Temperature Grade 3: –40°C to 85°C
- Stereo Audio DAC
- 102-dBA Signal-to-Noise Ratio
- 16-, 20-, 24-, or 32-Bit Data
- Supports Rates From 8 kHz to 96 kHz
- 3D, Bass, Treble, EQ, De-Emphasis Effects
- Flexible Power Saving Modes and
Performance are Available
- Stereo Audio ADC
- 92-dBA Signal-to-Noise Ratio
- Supports Rates From 8 kHz to 96 kHz
- Digital Signal Processing and Noise Filtering
Available During Record
- Ten Audio Input Pins
- Programmable in Single-Ended or Fully
Differential Configurations - 3-State Capability for Floating Input
Configurations
- Programmable in Single-Ended or Fully
- Seven Audio Output Drivers
- Stereo Fully Differential or Single-Ended
Headphone Drivers - Fully Differential Stereo Line Outputs
- Fully Differential Mono Output
- Stereo Fully Differential or Single-Ended
- Low Power: 15-mW Stereo 48-kHz Playback With
3.3-V Analog Supply - Ultralow-Power Mode with Passive Analog Bypass
- Programmable I/O Analog Gains
- Programmable PLL for Flexible Clock Generation
- Control Bus Selectable SPI or I2C
- Audio Serial Data Bus Supports I2S, Left/Right-
Justified, DSP, and TDM Modes - Power Supplies:
- Analog: 2.7 V to 3.6 V
- Digital Core: 1.65 V to 1.95 V
- Digital I/O: 1.1 V to 3.6 V
The TLV320AIC3106-Q1 is a low-power stereo audio codec with stereo headphone amplifier, as well as multiple inputs and outputs programmable in single-ended or fully differential configurations. Extensive register-based power control is included, enabling stereo 48-kHz DAC playback as low as 15 mW from a 3.3-V analog supply, making it ideal for car audio applications in cluster and head unit systems.
The record path of the TLV320AIC3106-Q1 contains integrated microphone bias, digitally controlled stereo microphone preamplifier, and automatic gain control (AGC), with mix and mux capability among the multiple analog inputs. Programmable filters are available during record which can remove audible noise that can occur in unpredictable environments, such as when an eCall system is activated. The playback path includes mix and mux capability from the stereo DAC and selected inputs, through programmable volume controls, to the various outputs.
The TLV320AIC3106-Q1 contains four high-power output drivers as well as three fully differential output drivers. The high-power output drivers are capable of driving a variety of load configurations, including up to four channels of single-ended 16-Ω headphones using AC-coupling capacitors, or stereo 16-Ω headphones in a capacitorless output configuration. These parameters enable the TLV320AIC3106-Q1 to act as an interface from the MCU to the speaker amplifiers, such as the TPA3111D1-Q1, in various audio applications in infotainment and clusters.
The stereo audio DAC supports sampling rates from 8 kHz to 96 kHz and includes programmable digital filtering in the DAC path for 3D, bass, treble, midrange effects, speaker equalization, and de-emphasis for 32-kHz, 44.1-kHz, and 48-kHz rates. The stereo audio ADC supports sampling rates from 8 kHz to 96 kHz and is preceded by programmable gain amplifiers or AGC that can provide up to 59.5-dB analog gain for low-level microphone inputs. The TLV320AIC3106-Q1 provides an extremely high range of programmability for both attack (8?ms to 1408 ms) and for decay (0.05 s to 22.4 s). This extended AGC range allows the AGC to be tuned for many types of applications.
The serial control bus supports SPI or I2C protocols, while the serial audio data bus is programmable for I2S, left/right-justified, DSP, or TDM modes. A highly programmable PLL is included for flexible clock generation and support for all standard audio rates from a wide range of available MCLKs, varying from 512 kHz to 50 MHz, with special attention paid to the most popular cases of 12-MHz, 13-MHz, 16-MHz, 19.2-MHz, and 19.68-MHz system clocks.
The TLV320AIC3106-Q1 operates from an analog supply of 2.7 V to 3.6 V, a digital core supply of 1.65 V to 1.95?V, and a digital I/O supply of 1.1 V to 3.6 V. The device is available in the 7-mm × 7-mm, 48-lead VQFN (RGZ) package.
