Efficient DSP Algorithm Develo

Introduction
The use of Digital Signal Processing (DSP) in electronic products is increasing at a phenomenal rate. Field-
Programmable Gate Arrays (FPGAs), with their multi-million equivalent gate counts and DSP-centric features can
offer dramatic performance increases over standard DSP chips. They also offer an attractive alternative for small
and medium volume production  FPGAs also make very powerful prototyping and verification vehicles for real-
time emulation of DSP algorithms [1].
This paper discusses the challenges and requirements of creating portable algorithmic IP for FPGAs and ASICs
and illustrates how an ESL synthesis methodology using the Synplify® DSP tool can significantly reduce the time
and effort to implement either technology.  The Synplify DSP tool automatically creates optimized logic imple-
mentations for both FPGAs and ASICs.