资料介绍
Table of Contents
AD9467 Evaluation Board, ADC-FMC Interposer & Xilinx Reference Design
Introduction
The AD9467 is a 16-bit, monolithic, IF sampling analog-to-digital converter (ADC) with a conversion rate of up to 250MSPS. This reference design includes the device data capture and SPI interface. The samples are written to the external DDR-DRAM on ML605. It allows programming the device and monitoring its internal registers via SPI. It also allows programming the AD9517-4 clock chip as an alternative clock source on the board. The board also provides other options to drive the clock to the ADC.
Supported Devices
Supported Carriers
Quick Start Guide
The reference design has been tested with ML605, KC705 and VC707. The notes below refer to ML605, the procedure is same for the other boards. Please make sure you are using the correct reference design for the board(s) that you have. The bit file provided combines the FPGA bit file and the SDK elf files. It may be used for a quick check on the system. All you need is the hardware and a PC running a UART terminal and the programmer (IMPACT).
Required Hardware
- ML605, KC705 or VC707 board
- AD9467-2x0EBZ board & Power supply
- ADC FMC interposer board
- Signal/Clock generator (clock input, 200MHz or 250MHz)
- Signal generator (analog input, for data capture)
Required Software
- Xilinx ISE 13.2 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
- A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.
Bit file
- Download the gzip file and extract the sw/cf_ad9467_ebz.bit file.
Board Modifications
If you have a Rev. A version of the FMC interposer board, please do the following modifications on the board.
- Populate R209 (0ohm) and make sure R211 is NOT populated.
- Insert (cut the traces) 33ohm resistors on U201 (UG3308) Y ports (pins 11 through 17).
- Make sure that R201 through R207 are NOT populated.
If you have a Rev. A version of the AD9467 evaluation board, please do the following modifications on the board.
- Remove R309 on pin 14 of AD9517 (U300).
- Remove R600 on pin 3 of NC7WZ16P (U601).
- Remove R601 on pin 1 of NC7WZ16P (U601).
- Remove R602 on pin 1 of NC7WZ07P (U600).
Running Demo (SDK) Program
To begin make the following connections (see image below):
- Connect the AD9467-2x0EBZ board to the FMC Interposer board.
- Connect the interposer board to the FMC-HPC connector of ML605 board.
- Connect power to ML605 and the AD9467-2x0EBZ boards.
- Connect two USB cables from the PC to the JTAG and UART USB connectors on ML605.
- Connect an external clock source to AD9467-2x0EBZ board's J201 SMA connector.
- Connect a signal generator to the AIN SMA J100 SMA connector.
If you have AD9467-200EBZ board setup the clock source to be 200MHz, if AD9467-250EBZ set up the clock source to be 250MHz. This quick start bit file configures the AD9467 for all test modes and verifies the captured data accordingly. After the hardware setup, turn the power on to the ML605 and the AD9467-2x0EBZ boards.
Start IMPACT, and initialze the JTAG chain. The program should recognize the Virtex 6 device (see screenshot below). Start a UART terminal (set to 57600 baud rate) and then program the device.
If programming was successful, you should be seeing messages appear on the terminal as shown in figure below. After programming the AD9467 and AD9517, the program checks data capture on various test modes. Please note that AD9517 is powered down by default but is still accessable via SPI.
After patterns and prbs sequences are verified, if no errors are present, you may use the chipscope busplot to see the captured signal (see below). The ADC data is available on pins [15:0] of the chipscope signal.
Using the reference design
The reference design is built on a microblaze based system parameterized for linux. A functional block diagram of the design is given below.
Xilinx block diagram
AD9467 FMC Card block diagram
The reference design consists of three functional modules, a LVDS interface, a PN9/PN23/PAT monitor and a DMA interface.
The LVDS interface captures and buffers data from the ADC. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software.
Registers
Please refer to the regmap.txt file in the pcores directory.
Good To Know
The PN9/PN23 sequences are not compatible with O.150. Please use the equations given in the reference design. They follow the polynomial equations as in O.150, but ONLY the msb is inverted.
The AD9467 drives the interleaved first byte (D15:D1) on the rising edge and second byte (D14:D0) on the falling edge of DCO clock. However in certain frequencies the captured data (from IDDR) seems to be reverse. If that occurs try setting the “capture select” bit (register 0x0a, bit 0).
Clock Selection
There are several clock paths available on the evaluation board.
Downloads
FPGA Referece Designs:
Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See generating Xilinx netlist/verilog files from xco files for details.
- Questions? Ask Help & Support.
Tar file contents
The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to Xilinx EDK documentation for details.
license.txt | ADI license & copyright information. |
system.mhs | MHS file. |
system.xmp | XMP file (use this file to build the reference design). |
data/ | UCF file and/or DDR MIG project files. |
docs/ | Documentation files (Please note that this wiki page is the documentation for the reference design). |
sw/ | Software (Xilinx SDK) & bit file(s). |
cf_lib/edk/pcores/ | Reference design core file(s) (Xilinx EDK). |
More information
- AD9467 SIMULINK ADIsimADC模型 0次下载
- AD9467 BOM表 22次下载
- FMC插入器&Xilinx KC705参考设计 13次下载
- AD7656-1 FMC-SDP转接器和评估板/Xilinx KC705参考设计 12次下载
- AD7658-1 FMC-SDP转接器和评估板/Xilinx KC705参考设计 7次下载
- ADC-FMC插入器&Xilinx ZC706参考设计 7次下载
- AD9833 FMC-SDP转接器和评估板/Xilinx KC705参考设计 11次下载
- AD9129评估板、DAC-FMC插入器和Xilinx ML-605参考设计 11次下载
- AD9671评估板、ADC-FMC转接器和Xilinx KC705参考设计 2次下载
- AD5780 FMC-SDP转接器和评估板/Xilinx KC705参考设计 8次下载
- AD9250评估板、ADC-FMC转接器和Xilinx KC705参考设计 3次下载
- AD9279评估板、ADC-FMC转接器和Xilinx ML605参考设计 12次下载
- AD9739A评估板、DAC-FMC插入器和Xilinx参考设计 7次下载
- AD9122评估板、DAC-FMC插入器和Xilinx ML-605参考设计 8次下载
- AD9467:16位,200 MSPS/250 MSPS类比数字Converator数据Sheet 4次下载
- 怎么评估ADC的SFDR和中频滤波器的抑制度呢? 265次阅读
- ADC眼中的虚拟评估,第2部分 404次阅读
- 关于高速ADC测试和评估应用 854次阅读
- 了解光纤通信的插入损耗和回拨损耗 1w次阅读
- Xilinx FPGA的FMC介绍 5127次阅读
- digilent FMC Pcam适配器介绍 2497次阅读
- 2.5 GSPS高性能数模转换器——AD9739A DAC 4275次阅读
- 关于FPGA的FMC接口的详细介绍 1.1w次阅读
- 采用Xilinx ML507评估平台的APU增强型FPGA设计 1109次阅读
- 基于Xilinx reVISION Stack Demo双摄像头采集图像 3117次阅读
- 评估license的申请途径和方法介绍 4514次阅读
- ADI AD4002 18位2 MSPS SAR ADC评估方案详解 5587次阅读
- 基于FPGA 的FMC 接口应用实例 9709次阅读
- stm32案例分享之使D-CACHE时FMC外设运行不正常原因 9799次阅读
- Maxim为三款Xilinx FPGA参考设计提供电源管理方案 1114次阅读
下载排行
本周
- 1UHD智能显示SoC VS680产品简介
- 0.46 MB | 7次下载 | 免费
- 2深蕾半导体智能显示SoC芯片 VS680产品简介
- 0.33 MB | 3次下载 | 免费
- 3JW7707F杰华特3.4A50V,7mΩ同步整流器-jw7707f参数规格书
- 268.87 KB | 2次下载 | 免费
- 4电池管理系统(BMS)软硬件介绍
- 0.23 MB | 2次下载 | 2 积分
- 5分析电源电感发热解决方法
- 0.26 MB | 2次下载 | 免费
- 6大功率LED驱动器DW8501数据手册
- 0.37 MB | 1次下载 | 2 积分
- 74.5V 至 52V 输入、电流模式升压控制器TPS4021x-Q1数据表
- 2.03MB | 1次下载 | 免费
- 8电压检测芯片TPS3803和TPS3805数据表
- 1.06MB | 1次下载 | 免费
本月
- 1DCDC原理详解
- 0.98 MB | 85次下载 | 免费
- 2FU-7(807)胆机原理图
- 11.93 MB | 26次下载 | 1 积分
- 3电子元件基础知识介绍
- 8.76 MB | 26次下载 | 2 积分
- 4用于汽车应用的高压电源管理IC TPS65311-Q1数据表
- 1.05MB | 22次下载 | 免费
- 5DC-DC电路(Buck)的设计与仿真
- 0.60 MB | 12次下载 | 2 积分
- 6GD32F10x系列MCU用户手册
- 11.5MB | 9次下载 | 免费
- 7多功能电源管理 SOC IP5306数据手册
- 0.20 MB | 7次下载 | 免费
- 8UHD智能显示SoC VS680产品简介
- 0.46 MB | 7次下载 | 免费
总榜
- 1matlab软件下载入口
- 未知 | 935083次下载 | 免费
- 2开源硬件-PMP21529.1-4 开关降压/升压双向直流/直流转换器 PCB layout 设计
- 1.48MB | 420046次下载 | 免费
- 3Altium DXP2002下载入口
- 未知 | 233067次下载 | 免费
- 4电路仿真软件multisim 10.0免费下载
- 340992 | 191314次下载 | 免费
- 5十天学会AVR单片机与C语言视频教程 下载
- 158M | 183311次下载 | 免费
- 6labview8.5下载
- 未知 | 81567次下载 | 免费
- 7Keil工具MDK-Arm免费下载
- 0.02 MB | 73786次下载 | 免费
- 8NI LabVIEW中实现3D视觉的工具和技术
- 未知 | 70088次下载 | 免费
评论
查看更多