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| 软件名称 |
CY7C4425/CY7C4205/CY7C4215 pdf datasheet |
| 运行环境 |
Win9X/Win2000/WinXP/Win2003/ |
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| 整理时间 |
2008-8-29 14:51:19 |
| 软件星级 |
 |
| 软件语言 |
简体中文 |
| 软件类型 |
国产软件 |
| 授权方式 |
共享软件 |
| 软件大小 |
555 KB |
| 相关连接 |
csb23@126.com 官方主页 没有预览图片
[收 藏] |
| 下载统计 |
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| 解压密码 |
www.elecfans.com |
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 软件简介 |
The CY7C42X5 are high-speed, low-power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All
are 18 bits wide and are pin/functionally compatible to
IDT722x5. The CY7C42X5 can be cascaded to increase FIFO
depth. Programmable features include Almost Full/Almost
Empty flags. These FIFOs provide solutions for a wide variety
of data buffering needs, including high-speed data acquisition,
multiprocessor interfaces, and communications buffering.
These FIFOs have 18-bit input and output ports that are controlled
by separate clock and enable signals. The input port iscontrolled by a free-running clock (WCLK) and a write enable
pin (WEN).
When WEN is asserted, data is written into the FIFO on the
rising edge of the WCLK signal. While WEN is held active, data
is continually written into the FIFO on each cycle. The output
port is controlled in a similar manner by a free-running read
clock (RCLK) and a read enable pin (REN). In addition, the
CY7C42X5 have an output enable pin (OE). The read and
write clocks may be tied together for single-clock operation or
the two clocks may be run independently for asynchronous
read/write applications. Clock frequencies up to 100 MHz are
achievable.
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