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| 软件名称 |
CY27EE16ZE pdf datasheet |
| 运行环境 |
Win9X/Win2000/WinXP/Win2003/ |
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| 整理时间 |
2008-7-21 14:33:48 |
| 软件星级 |
 |
| 软件语言 |
简体中文 |
| 软件类型 |
国产软件 |
| 授权方式 |
共享软件 |
| 软件大小 |
667 KB |
| 相关连接 |
csb23@126.com 官方主页 没有预览图片
[收 藏] |
| 下载统计 |
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| 解压密码 |
www.elecfans.com |
|
 软件简介 |
The CY27EE16ZE integrates a 16-kbit EEPROM scratchpad
and a clock generator that features Cypress’s programmable
clock core. An industry standard I
2C serial programming
interface (SPI) is used to program the scratchpad and clock
core.
16-kbit EEPROM
The 16-kbit EEPROM scratchpad is organized in eight blocks
x 256 words x 8 bits. Each of the eight 2-kbit EEPROM
scratchpad blocks, a 2-kbit clock configuration EEPROM
block, and a 2-kbit volatile clock configuration SRAM block,
have their own 7-bit device address. The device address is
combined with a Read/Write bit as the LSB and is sent after
each start bit.
Clock Features
The programmable clock core is configured with the following
features:
• Crystal Oscillator: Programmable drive and load, support
for external references up to 166 MHz. See "Reference
Frequency (REF)", page 5
• VCX Analog or digital control
• Inputs and I/Os: Programmable input muxes drive write
protect (WP), analog VCXO control, output enable (OE),
and power down mode (PDM) functions
• PLL: Programmable P, Q, offset, and loop filter parameters.
Outputs: Six outputs and two programmable linear dividers.
The output swing of CLOCK1 through CLOCK4 is set by VDDL
(2.5V or 3.3V). The output swing of CLOCK5 and CLOCK6 is
set by VDD (3.3V).
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| CY27EE16ZE pdf datasheet下载页面 |
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