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| 软件名称 |
UDA1355/UDA1355H pdf datasheet |
| 运行环境 |
Win9X/Win2000/WinXP/Win2003/ |
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| 整理时间 |
2008-7-16 16:34:16 |
| 软件星级 |
 |
| 软件语言 |
简体中文 |
| 软件类型 |
国产软件 |
| 授权方式 |
共享软件 |
| 软件大小 |
66 KB |
| 相关连接 |
3 官方主页 没有预览图片
[收 藏] |
| 下载统计 |
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| 解压密码 |
www.elecfans.com |
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 软件简介 |
The UDA1355H is a single-chip IEC 60958 decoder and
encoder with integrated stereo digital-to-analog converters
and analog-to-digital converters employing bitstream
conversion techniques.
The UDA1355H has a selectable one-of-four SPDIF input
(accepting level I, II and III timing) and one SPDIF outputwhich can generate level II output signals with CMOS
levels. In microcontroller mode the UDA1355H offers a
large variety of possibilities for defining signal flows
through the IC, offering a flexible analog, digital and SPDIF
converter chip with possibilities for off-chip sound
processing via the digital input and output interface.
A lock indicator is available on pin LOCK when the
IEC 60958 decoder and the clock regeneration
mechanism is in lock. By default the DAC output and the
digital data interface output are muted when the decoder
is not in lock.
The UDA1355H contains two clock systems which can run
at independent frequencies, allowing to lock-on to an
incoming SPDIF or digital audio signal, and in the mean
time generating a stable signal by means of the crystal
oscillator for driving, for example, the ADC or SPDIF
output signal.
Using the crystal oscillator (which requires a 12.288 MHz
crystal) and the on-chip low jitter PLL, all standard audio
sampling frequencies (fs = 32, 44.1 and 48 kHz including
half and double these frequencies) can be generated.
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