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SMJ320C6415 定点数字信号处理器

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描述

TMS320C64x ?? DSP(包括SMJ320C6414,SMJ320C6415和SMJ320C6416器件)是TMS320C6000中性能最高的定点DSP产品? DSP平台。 TMS320C64x ?? (C64x ?? )设备是基于第二代高性能,先进的VelociTI ??德州仪器(TI)开发的超长指令字(VLIW)架构(VelociTI.2 ??),使这些DSP成为多通道和多功能应用的绝佳选择。 C64x ??是C6000的代码兼容成员?? DSP平台。

C64x器件以720 MHz的时钟速率提供高达57.6亿条指令/秒(MIPS)的性能,可为高性能DSP编程挑战提供经济高效的解决方案。 C64x DSP具有高速控制器的操作灵活性和阵列处理器的数字功能。 C64x ?? DSP内核处理器有64个32位字长的通用寄存器和8个高度独立的功能单元 - 两个乘法器用于32位结果和六个算术逻辑单元(ALU)??用VelociTI.2 ??扩展。 VelociTI.2 ??八个功能单元中的扩展包括新的指令,以加速关键应用程序的性能,并扩展VelociTI的并行性?建筑。 C64x每周期可产生4个32位乘法累加(MAC),总计每秒2400万MAC(MMACS),或每周期8个8位MAC,总计4800 MMACS。 C64x DSP还具有特定于应用的硬件逻辑,片上存储器以及与其他C6000类似的其他片上外设。 DSP平台设备。

C6416器件具有两个高性能嵌入式协处理器[Viterbi解码器协处理器(VCP)和Turbo解码器协处理器(TCP)],可显着加速片上通道解码操作。以CPU时钟4分频运行的VCP可以解码超过500个7.95-Kbps自适应多速率(AMR)[K = 9,R = 1/3]语音信道。 VCP支持约束长度K = 5,6,7,8和9,速率R = 1 /2,1 /3和1/4,以及灵活多项式,同时产生硬判决或软判决。以CPU时钟2分频运行的TCP可以解码多达36个384-Kbps或6个2-Mbps turbo编码信道(假设6次迭代)。 TCP实现max * log-map算法,旨在支持第三代合作伙伴计划(3GPP和3GPP2)所需的所有多项式和速率,具有完全可编程帧长度和turbo交织器。解码参数(例如迭代次数和停止标准)也是可编程的。 VCP /TCP与CPU之间的通信通过EDMA控制器进行。

C64x采用基于缓存的两级架构,具有强大而多样的外设集。 1级程序高速缓存(L1P)是128-Kbit直接映射高速缓存,1级数据高速缓存(L1D)是128-Kbit 2路组关联高速缓存。 2级内存/高速缓存(L2)由8 Mbit的内存空间组成,在程序和数据空间之间共享。 L2内存可以配置为映射内存或缓存(最多256K字节)和映射内存的组合。外设集包括三个多通道缓冲串行端口(McBSP);用于异步传输模式(ATM)从设备[UTOPIA从设备]端口的8位通用测试和操作PHY接口(仅限C6415 /C6416);三个32位通用定时器;用户可配置的16位或32位主机端口接口(HPI16 /HPI32);外围组件互连(PCI)[仅限C6415 /C6416];具有16个GPIO引脚的通用输入/输出端口(GPIO);和两个无胶外部存储器接口(64位EMIFA和16位EMIFB ),两者都是能够连接同步和异步存储器和外设。

C64x有一套完整的开发工具,包括:具有C64x特定增强功能的高级C编译器,简化编程和调度的汇编优化器,以及一个Windows?调试器接口,用于查看源代码执行。

特性

  • Highest-Performance Fixed-Point Digital Signal Processors (DSPs)
    • 2-, 1.67-, 1.39-ns Instruction Cycle Time
    • 600-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • Twenty-Eight Operations/Cycle
    • 4800 MIPS
    • Fully Software-Compatible With C62x™
    • C6414/15/16 Devices Pin-Compatible
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers SupportFour 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Non-Aligned Load-Store Architecture
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2™ Increased Orthogonality
  • Viterbi Decoder Coprocessor (VCP) [C6416]
    • Supports Over 500 7.95-Kbps AMR
    • Programmable Code Parameters
  • Turbo Decoder Coprocessor (TCP) [C6416]
    • Supports up to Six 2-Mbps 3GPP (6 Iterations)
    • Programmable Turbo Code and Decoding Parameters
  • L1/L2 Memory Architecture
    • 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
    • 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 8M-Bit (1024K-Byte) L2 Unified Mapped RAM/Cache (Flexible Allocation)
  • Two External Memory Interfaces (EMIFs)
    • One 64-Bit (EMIFA), One 16-Bit (EMIFB)
    • Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
    • 1280M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • Host-Port Interface (HPI)
    • User-Configurable Bus Width (32-/16-Bit)
  • 32-Bit/33-MHz, 3.3-V PCI Master/Slave Interface Conforms to PCI Specification 2.2 [C6415/C6416 ]
    • Three PCI Bus Address Registers:
          Prefetchable Memory
          Non-Prefetchable Memory I/O
    • Four-Wire Serial EEPROM Interface
    • PCI Interrupt Request Under DSP Program Control
    • DSP Interrupt Via PCI I/O Cycle
  • Three Multichannel Buffered Serial Ports
    • Direct Interface to T1/E1, MVIP, SCSA Framers
    • Up to 256 Channels Each
    • ST-Bus-Switching-, AC97-Compatible
    • Serial Peripheral Interface (SPI) Compatible (Motorola™)
  • Three 32-Bit General-Purpose Timers
  • Universal Test and Operations PHY Interface for ATM (UTOPIA) [C6415/C6416]
    • UTOPIA Level 2 Slave ATM Controller
    • 8-Bit Transmit and Receive Operations up to 50 MHz per Direction
    • User-Defined Cell Format up to 64 Bytes
  • Sixteen General-Purpose I/O (GPIO) Pins
  • Flexible PLL Clock Generator
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 570-Pin Grid Array (PGA) Package (GAD Suffix)
  • 0.13-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V I/Os, 1.4-V Internal

C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C6000, C64x, and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
All trademarks are the property of their respective owners.
Throughout the remainder of this document, the SMJ320C6414, SMJ320C6415, and SMJ320C6416 shall be referred to as SMJ320C64x or C64x where generic, and where specific, their individual full device part numbers will be used or abbreviated as C6414, C6415, or C6416.
These C64x™ devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix &quote;A&quote; in front of a signal name indicates it is an EMIFA signal whereas a prefix &quote;B&quote; in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix &quote;A&quote; or &quote;B&quote; may be omitted from the signal name.

参数 与其它产品相比 C6000 DSP

 
DSP
On-Chip L2 Cache/RAM
Operating Temperature Range (C)
Rating
SMJ320C6415 SM320C6415
  1 C64x    
1024 KB     1024 KB    
-55 to 115     -55 to 115    
Military     Military    

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