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OMAP-L137 C6000 DSP+ARM 处理器

数据:

描述

OMAP-L137器件是一款基于ARM926EJ-S和TMS320C674x DSP内核的低功耗应用处理器。它的功耗显着低于DSP的TMS320C6000平台的其他成员。

OMAP-L137器件使原始设备制造商(OEM)和原始设计制造商(ODM)能够快速推向市场通过完全集成的混合处理器解决方案的最大灵活性,提供强大的操作系统支持,丰富的用户界面和高处理性能。

OMAP-L137器件的双核架构提供了DSP和DSP的优势。精简指令集计算机(RISC)技术,集成了高性能TMS320C674x DSP内核和ARM926EJ-S内核。

ARM926EJ-S是一个32位RISC处理器内核,可执行32位或16位位指令和处理32位,16位或8位数据。核心使用流水线操作,以便处理器和内存系统的所有部分可以连续运行。

ARM内核具有协处理器15(CP15),保护模块以及数据和程序内存管理单元(MMU)表后备缓冲区。 ARM内核具有单独的16 KB指令和16 KB的数据高速缓存。两个内存块都与虚拟索引虚拟标记(VIVT)进行四向关联。 ARM内核还具有8KB的RAM(向量表)和64KB的ROM。

OMAP-L137 DSP内核使用基于高速缓存的两级架构。 1级程序高速缓存(L1P)是32 KB直接映射高速缓存,1级数据高速缓存(L1D)是32 KB双向组关联高速缓存。 2级程序高速缓存(L2P)由256 KB内存空间组成,在程序和数据空间之间共享。 L2内存可以配置为映射内存,缓存或两者的组合。尽管ARM L2和系统中的其他主机可以访问DSP L2,但是其他主机可以使用额外的128KB RAM共享内存,而不会影响DSP性能。

外设集包括:带管理数据输入/输出(MDIO)模块的10/100 Mbps以太网MAC(EMAC);两个I 2 C总线接口; 3个多声道音频串行端口(McASP),带有16/12/4串行器和FIFO缓冲器;两个64位通用定时器,每个都可配置(一个可配置为看门狗);可配置的16位主机端口接口(HPI);多达8个16引脚的通用输入/输出(GPIO),具有可编程中断/事件生成模式,与其他外设复用; 3个UART接口(一个具有 RTS CTS );三个增强型高分辨率脉冲宽度调制器(eHRPWM)外设;三个32位增强型捕获(eCAP)模块外设,可配置为3个捕获输入或3个辅助脉冲宽度调制器(APWM)输出;两个32位增强型正交编码脉冲(eQEP)外设;和2个外部存储器接口:用于较慢存储器或外设的异步和SDRAM外部存储器接口(EMIFA),以及用于SDRAM的高速存储器接口(EMIFB)。

以太网媒体访问控制器(EMAC)提供OMAP-L137设备与网络之间的高效接口。 EMAC支持10Base-T和100Base-TX,或半双工或全双工模式下的10 Mbps和100 Mbps。此外,MDIO接口可用于PHY配置。

HPI,I2C,SPI,USB1.1和USB2.0端口允许OMAP-L137设备轻松控制外围设备和/或与主机处理器通信。

丰富的外设集提供了控制外部外围设备和与外部处理器通信的能力。有关每个外设的详细信息,请参阅本文档后面的相关章节以及相关的外设参考指南。

OMAP-L137器件具有一整套用于ARM和DSP的开发工具。这些包括C编译器,用于简化编程和调度的DSP汇编优化器,以及用于查看源代码执行的Windows®调试器接口。

特性

  • Software Support
    • TI DSP/BIOS
    • Chip Support Library and DSP Library
  • Dual Core SoC
    • 375- and 456-MHz ARM926EJ-S RISC MPU
    • 375- and 456-MHz C674x VLIW DSP
  • ARM926EJ-S Core
    • 32-Bit and 16-Bit (Thumb®) Instructions
    • DSP Instruction Extensions
    • Single Cycle MAC
    • ARM® Jazelle® Technology
    • Embedded ICE-RT™ for Real-Time Debug
  • ARM9™ Memory Architecture
    • 16KB of Instruction Cache
    • 16KB of Data Cache
    • 8KB of RAM (Vector Table)
    • 64KB of ROM
  • C674x Instruction Set Features
    • Superset of the C67x+ and C64x+ ISAs
    • Up to 3648 MIPS and 2736 MFLOPS C674x
    • Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
  • C674x Two-Level Cache Memory Architecture
    • 32KB of L1P Program RAM/Cache
    • 32KB of L1D Data RAM/Cache
    • 256KB of L2 Unified Mapped RAM/Cache
    • Flexible RAM/Cache Partition (L1 and L2)
  • Enhanced Direct Memory Access Controller 3 (EDMA3):
    • 2 Transfer Controllers
    • 32 Independent DMA Channels
    • 8 Quick DMA Channels
    • Programmable Transfer Burst Size
  • TMS320C674x Fixed- and Floating-Point VLIW DSP Core
    • Load-Store Architecture with Nonaligned Support
    • 64 General-Purpose Registers (32-Bit)
    • Six ALU (32- and 40-Bit) Functional Units
      • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
      • Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks
      • Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
    • Two Multiply Functional Units
      • Mixed-Precision IEEE Floating Point Multiply Supported up to:
        • 2 SP x SP -> SP Per Clock
        • 2 SP x SP -> DP Every Two Clocks
        • 2 SP x DP -> DP Every Three Clocks
        • 2 DP x DP -> DP Every Four Clocks
      • Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Hardware Support for Modulo Loop
      Operation
    • Protected Mode Operation
    • Exceptions Support for Error Detection and Program Redirection
  • 128KB of RAM Shared Memory
  • 3.3-V LVCMOS I/Os (Except for USB Interfaces)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8- or 16-Bit-Wide Data)
      • NAND (8- or 16-Bit-Wide Data)
      • 16-Bit SDRAM with 128-MB Address Space
    • EMIFB
      • 32-Bit or 16-Bit SDRAM with 256-MB Address Space
  • Three Configurable 16550-Type UART Modules:
    • UART0 with Modem Control Signals
    • Autoflow Control Signals (CTS, RTS) on UART0 Only
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
  • LCD Controller
  • Two Serial Peripheral Interfaces (SPIs) Each with One Chip Select
  • Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)
  • Two Master and Slave Inter-Integrated Circuit (I2C Bus™)
  • One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address/Data Bus for High Bandwidth
  • Programmable Real-Time Unit Subsystem (PRUSS)
    • Two Independent Programmable Realtime Unit (PRU) Cores
      • 32-Bit Load and Store RISC Architecture
      • 4KB of Instruction RAM per Core
      • 512 Bytes of Data RAM per Core
      • PRUSS can be Disabled via Software to Save Power
    • Standard Power-Management Mechanism
      • Clock Gating
      • Entire Subsystem Under a Single PSC Clock Gating Domain
    • Dedicated Interrupt Controller
    • Dedicated Switched Central Resource
  • USB 1.1 OHCI (Host) with Integrated PHY (USB1)
  • USB 2.0 OTG Port with Integrated PHY (USB0)
    • USB 2.0 High- and Full-Speed Client
    • USB 2.0 High-, Full-, and Low-Speed Host
    • End Point 0 (Control)
    • End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
  • Three Multichannel Audio Serial Ports (McASPs):
    • Six Clock Zones and 28 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • DIT-Capable (McASP2)
    • FIFO Buffers for Transmit and Receive
  • 10/100 Mbps Ethernet MAC (EMAC):
    • IEEE 802.3 Compliant (3.3-V I/O Only)
    • RMII Media-Independent Interface
    • Management Data I/O (MDIO) Module
  • Real-Time Clock with 32-kHz Oscillator and Separate Power Rail
  • One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
  • Three Enhanced Pulse Width Modulators (eHRPWMs):
    • Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
    • 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
    • Dead-Band Generation
    • PWM Chopping by High-Frequency Carrier
    • Trip Zone Input
  • Three 32-Bit Enhanced Capture (eCAP) Modules:
    • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
    • Single-Shot Capture of up to Four Event Time-Stamps
  • Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
  • 256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
  • Commercial, Industrial, Extended, or Automotive Temperature

参数 与其它产品相比 音频处理器

 
DSP
DSP MHz (Max)
Arm CPU
Arm MHz (Max.)
Operating Systems
DRAM
On-Chip L2 Cache/RAM
Approx. Price (US$)
McASP
McBSP
USB
EMAC
Package Group
PCI/PCIe
I2C
UART (SCI)
DSP MMACS
Other Hardware Acceleration
OMAP-L137
1 C674x    
456    
1 ARM9    
456    
Linux
TI RTOS    
SDRAM    
256 KB (DSP)    
14.30 | 1ku    
3    
0    
2    
10/100    
BGA    
N/A    
2    
3    
3648    
PRU-ICSS    

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