Andes公司推出了Linux友好型A25CPU内核的新A25MP和AX25MP版本，这些内核被称为是首个带有“综合”DSP的RISC-V内核。1GHz以上的内核提供了缓存一致性，并支持SMP和多达四核设计。
在台湾RISC-V研讨会上，Andes技术公司宣布了其Linux友好型，兼容RISC-VISA的第二代A25（32位）和AX25（64位）CPU内核。Andes说，32位，28nm的A25MP和64位AX25MP是首批具有全面DSP指令扩展功能的商业RISC-V内核。与早期的A25代（请参阅下文）不同，它们也是第一个提供缓存一致性以支持多核和多处理器支持的产品。但是，最初的产品将是单核设计。
A25MP/AX25MPDSP（数字信号处理器）ISA基于Andes捐赠给RISC-V基金会的RISC-VP扩展草案（PDF）。台湾的Andes公司说，DSP在加速语音，音频和图像处理方面特别有用。该公司还指出了“增强人工智能和高级驾驶员辅助系统（ADAS）等应用程序的功能”。
与该公司的编译器，DSP库和模拟器一起使用时，A25MP/AX25MPDSP“在PNET中为MtCNN（多任务级联卷积网络）人脸检测和对齐算法提供了超过7倍的加速，”Andes说。DSP还据称在CIFAR10图像分类基准上提供了“数量级性能提升”，用于训练机器学习和计算机视觉算法。
适用于Linux的A25/AX25芯片的安第斯山脉CPUIP生态系统
体系结构图构成了新A25MP和AX25MP的基础
SoC设计人员可以使用DSPISA升级其现有的，具有Linux功能的A25和AX25芯片，Andes说。此外，安第斯山脉宣布了不具备Linux功能的32位D25F处理器，“这是不带MMU和S模式支持的A25”，它还提供了DSPISA。该公司表示，所有安第斯山脉的新处理器IP都“享受25系列处理器相同的有效基准管线以及用于定制指令设计的强大ACE工具”。
Andes公司早期的A25和AX25
在2018年10月，提供广泛的类似于MCU的RISC处理器的安第斯山脉（Andes）宣布了其首个具有开源RISC-VISA的内核。其中包括其微小的，非Linux兼容的N22和N25系列内核以及其首个Linux就绪的RISC-VIP：32位A25和64位AX25。
新的启用了DSP和多核的A25MP和AX25MP尚无文档，但它们可能会提供类似的单核非DSPA25和AX25上的所有功能。与Andes的基于RISC-V的N22和N25系列内核以及早期的非RISC-V部件一样，A25系列也是AndesCore系列的一部分，该系列“采用RISC-V作为第五代产品的子集”AndeStarV5体系结构。
A25和AX25看起来几乎完全相同，只是它们的32位和64位体系结构不同。Andes说，64位AX25支持需要访问地址空间超过4GB的高性能嵌入式应用程序。我们在比较规格表时看到的唯一区别是64位AX25在0.174平方毫米处相对于0.147平方毫米更大，而在22uW/MHz处则比17吸收更大的动态功率。
A25和AX25采用与新的多核DSP型号相同的台积电28nmHPC+工艺制造，具有5级流水线并支持高达1.2GHz，3.5CoreMark/MHz的性能。该处理器设计支持单精度和双精度浮点指令，半精度加载/存储，以及针对基于Linux的应用程序的MMU和Supervisor模式（S模式）。
A25和AX25提供分支预测，指令和数据缓存，用于低延迟访问的本地存储器以及对L1存储器软错误保护的ECC支持。其他功能包括PLIC和向量中断，AXI64位或AHB64/32位总线，以及用于低功耗和电源管理的PowerBrake和WFI模式。
开发工具包括AndeSightIDE，用于ACE的“COPILOT”工具以及JTAG和ICE调试。Andes为某些AndesCoreIP提供了AndesShape硬件开发平台，但到目前为止，这些都不支持A25系列。
SoC设计人员似乎可以使用A25和AX25IP，但是目前尚不清楚是否有任何基于A25的SoC交付。今年1月，该公司宣布，2018年内核已交付10亿片SoC，累计总计35亿片。但是，大多数（如果不是全部）都不使用RISC-V。
其他TuxifiedRISC-V芯片
A25内核家族加入了少量已发布的Linux就绪RISC-V内核，这些内核主要来自SiFive。该公司已将其内核扩展为对Linux友好的FreedomU540SoC，并宣布了下一代U74和U74-MC设计。
Microchip的Microsemi部门宣布了部分基于SiFive的U54-MC内核的Linux友好型PolarFireSoC。它被称为世界上第一个RISC-VFPGASOC。Shakti芯片是另一款受Linux支持的RISC-V芯片，该芯片部分由印度政府资助。
AndesTechnology没有为新的A25MP和AX25MPRISC-V内核提供可用性信息。
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信息描述The TLV1544 and TLV1548 are CMOS 10-bit switched-capacitor successive-approximation (SAR) analog-to-digital (A/D) converters. Each device has a chip select (CS\), input-output clock (I/O CLK), data input (DATA IN) and serial data output (DATA OUT) that provide a direct 4-wire synchronous serial peripheral interface (SPITM, QSPITM) port of a host microprocessor. When interfacing with a TMS320 DSP, an additional frame sync signal (FS) indicates the start of a serial data frame. The devices allow high-speed data transfers from the host. The (INV CLK)\ input provides further timing flexibility for the serial interface. In addition to a high-speed converter and versatile control capability, the device has an on-chip 11-channel multiplexer that can select any one of eight analog inputs or any one of three internal self-test voltages. The sample-and-hold function is automatic except for the extended sampling cycle,...
发表于 04-18 20:09 •
58次
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信息描述The TLV1544 and TLV1548 are CMOS 10-bit switched-capacitor successive-approximation (SAR) analog-to-digital (A/D) converters. Each device has a chip select (CS\), input-output clock (I/O CLK), data input (DATA IN) and serial data output (DATA OUT) that provide a direct 4-wire synchronous serial peripheral interface (SPITM, QSPITM) port of a host microprocessor. When interfacing with a TMS320 DSP, an additional frame sync signal (FS) indicates the start of a serial data frame. The devices allow high-speed data transfers from the host. The (INV CLK)\ input provides further timing flexibility for the serial interface. In addition to a high-speed converter and versatile control capability, the device has an on-chip 11-channel multiplexer that can select any one of eight analog inputs or any one of three internal self-test voltages. The sample-and-hold function is automatic except for the extended sampling cycle,...
发表于 04-18 20:09 •
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信息描述The TLV1570 is a 10-bit data acquisition system that combines an 8-channel input multiplexer (MUX), a high-speed 10-bit ADC, an on-chip reference, and a high-speed serial interface. The device contains an on-chip control register allowing control of channel selection, conversion start, reference voltage levels, and power down via the serial port. The MUX is independently accessible, which allows the user to insert a signal conditioning circuit such as an antialiasing filter or an amplifier, if required, between the MUX and the ADC. Therefore one signal conditioning circuit can be used for all eight channels.The TLV1570 operates from a single 2.7-V to 5.5-V power supply. The device accepts an analog input range from 0 V to AVDD and digitizes the input at a maximum 1.25 MSPS throughput rate. Power dissipation is only 8 mW with a 2.7-V supply or 40 mW with a 5.5-V supply. The device features an autopower-down mode that automatically ...
发表于 04-18 20:09 •
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信息描述The TLC1550x and TLC1551 are data acquisition analog-to-digital converters (ADCs) using a 10-bit, switched-capacitor, successive-approximation network. A high-speed, 3-state parallel port directly interfaces to a digital signal processor (DSP) or microprocessor (µP) system data bus. D0 through D9 are the digital output terminals with D0 being the least significant bit (LSB). Separate power terminals for the analog and digital portions minimize noise pickup in the supply leads. Additionally, the digital power is divided into two parts to separate the lower current logic from the higher current bus drivers. An external clock can be applied to CLKIN to override the internal system clock if desired. The TLC1550I and TLC1551I are characterized for operation from 40°C to 85°C. The TLC1550M is characterized over the full military range of 55°C to 125°C.特性Power Dissipation...40 mW Max Advanced LinEPIC Single-Po...
发表于 04-18 20:07 •
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信息描述The TLC1518 and TLC1514 are a family of high-performance, 10-bit, low power, 1.4 us, CMOS SAR analog-to-digital converters (ADC) which operate from a single 5 V power supply. These devices have three digital inputs and a 3-state output [chip select (CS\), serial input-output clock (SCLK), serial data input (SDI), and serial data output (SDO)] that provide a direct 4-wire interface to the serial port of most popular host microprocessors (SPI interface). When interfaced with a DSP, a frame sync (FS) signal is used to indicate the start of a serial data frame. In addition to a high-speed A/D converter and versatile control capability, these devices have an on-chip analog multiplexer that can select any analog inputs or one of three internal self-test voltages. The sample-and-hold function is automatically started after the fourth SCLK edge (normal sampling) or can be controlled by a special pin, CSTART\, to extend the sampl...
发表于 04-18 20:07 •
117次
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信息描述The TLC1518 and TLC1514 are a family of high-performance, 10-bit, low power, 1.4 us, CMOS SAR analog-to-digital converters (ADC) which operate from a single 5 V power supply. These devices have three digital inputs and a 3-state output [chip select (CS\), serial input-output clock (SCLK), serial data input (SDI), and serial data output (SDO)] that provide a direct 4-wire interface to the serial port of most popular host microprocessors (SPI interface). When interfaced with a DSP, a frame sync (FS) signal is used to indicate the start of a serial data frame. In addition to a high-speed A/D converter and versatile control capability, these devices have an on-chip analog multiplexer that can select any analog inputs or one of three internal self-test voltages. The sample-and-hold function is automatically started after the fourth SCLK edge (normal sampling) or can be controlled by a special pin, CSTART\, to extend the sampl...
发表于 04-18 20:07 •
124次
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信息描述The TLC1550x and TLC1551 are data acquisition analog-to-digital converters (ADCs) using a 10-bit, switched-capacitor, successive-approximation network. A high-speed, 3-state parallel port directly interfaces to a digital signal processor (DSP) or microprocessor (µP) system data bus. D0 through D9 are the digital output terminals with D0 being the least significant bit (LSB). Separate power terminals for the analog and digital portions minimize noise pickup in the supply leads. Additionally, the digital power is divided into two parts to separate the lower current logic from the higher current bus drivers. An external clock can be applied to CLKIN to override the internal system clock if desired. The TLC1550I and TLC1551I are characterized for operation from 40°C to 85°C. The TLC1550M is characterized over the full military range of 55°C to 125°C.特性Power Dissipation...40 mW Max Advanced LinEPIC Single-Po...
发表于 04-18 20:07 •
122次
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信息描述The THS12082 is a CMOS, low-power, 12-bit, 8 MSPS analog-to-digital converter (ADC). The speed, resolution, bandwidth, and single-supply operation are suited for applications in radar, imaging, high-speed acquisition, and communications. A multistage pipelined architecture with output error correction logic provides for no missing codes over the full operating temperature range. Internal control registers allow for programming the ADC into the desired mode. The THS12082 consists of two analog inputs, which are sampled simultaneously. These inputs can be selected individually and configured to single-ended or differential inputs. An integrated 16 word deep FIFO allows the storage of data in order to take the load off of the processor connected to the ADC. Internal reference voltages for the ADC (1.5 V and 3.5 V) are provided.An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the appl...
发表于 04-18 20:06 •
198次
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信息描述The THS1209 is a CMOS, low-power, 12-bit, 8 MSPS analog-to-digital converter (ADC). The speed, resolution, bandwidth, and single-supply operation are suited for applications in radar, imaging, high-speed acquisition, and communications. A multistage pipelined architecture with output error correction logic provides for no missing codes over the full operating temperature range. Internal control registers allow for programming the ADC into the desired mode. The THS1209 consists of two analog inputs, which are sampled simultaneously. These inputs can be selected individually and configured to single-ended or differential inputs. Internal reference voltages for the ADC (1.5 V and 3.5 V) are provided. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. The THS1209C is characterized for operation from 0°C to 70°C, and the THS1209I is characterized for operation from ...
发表于 04-18 20:06 •
199次
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信息描述The THS1207 is a CMOS, low-power, 12-bit, 6 MSPS analog-to-digital converter (ADC). The speed, resolution, bandwidth, and single-supply operation are suited for applications in radar, imaging, high-speed acquisition, and communications. A multistage pipelined architecture with output error correction logic provides for no missing codes over the full operating temperature range. Internal control registers are used to program the ADC into the desired mode. The THS1207 consists of four analog inputs, which are sampled simultaneously. These inputs can be selected individually and configured to single-ended or differential-inputs. Internal reference voltages for the ADC (1.5 V and 3.5 V) are provided. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. The THS1207C is characterized for operation from 0°C to 70°C, the THS1207Iis characterized for operation from 40°...
发表于 04-18 20:05 •
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信息 BelaSigna®R281是一款超低功耗语音触发解决方案，适用于各种消费电子设备。在典型的应用中，BelaSigna R281“始终在聆听”。并且将检测单个用户训练的触发短语，当检测到该触发短语时断言唤醒信号。 “始终开启”。平均功耗小于300 uW的关键短语检测（不包括麦克风的功耗）可保持待机电池寿命。 BelaSigna R281是一款超小型解决方案，可同时提供采用5 mm x 5mm QFN32封装和2.42 mm x 2.74 mm WLCSP封装。它可以设计在单层PCB上，具有4 mil布线和最少量的外部元件。 需要一个外部的I C主控制器来配置器件进行操作。 超低功耗 卓越绩效 混合信号 Easy Design-In 优势特点 主要功能 久经考验的超低功耗数字信号处理（DSP）技术 •最初为助听器开发的音频DSP技术在以下方面具备所需的计算能力极低电流消耗 •...
发表于 04-18 19:42 •
125次
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信息描述The THS10082 is a CMOS, low-power, 10-bit, 8 MSPS analog-to-digital converter (ADC). The speed, resolution, bandwidth, and single-supply operation are suited for applications in radar, imaging, high-speed acquisition, and communications. A multistage pipelined architecture with output error correction logic provides for no missing codes over the full operating temperature range. Internal control registers allow for programming the ADC into the desired mode. The THS10082 consists of two analog inputs, which are sampled simultaneously. These inputs can be selected individually and configured to single-ended or differential inputs. An integrated 16 word deep FIFO allows the storage of data in order to take the load off of the processor connected to the ADC. Internal reference voltages for the ADC (1.5 V and 3.5 V) are provided. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the app...
发表于 04-18 19:06 •
122次
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信息描述The THS1206 is a CMOS, low-power, 12-bit, 6 MSPS analog-to-digital converter (ADC). The speed, resolution, bandwidth, and single-supply operation are suited for applications in radar, imaging, high-speed acquisition, and communications. A multistage pipelined architecture with output error correction logic provides for no missing codes over the full operating temperature range. Internal control registers are used to program the ADC into the desired mode. The THS1206 consists of four analog inputs, which are sampled simultaneously. These inputs can be selected individually and configured to single-ended or differential inputs. An integrated 16 word deep FIFO allows the storage of data in order to take the load off of the processor connected to the ADC. Internal reference voltages for the ADC (1.5 V and 3.5 V) are provided. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the applic...
发表于 04-18 19:06 •
157次
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信息描述 The THS1007 is a CMOS, low-power, 10-bit, 6 MSPS analog-to-digital converter (ADC). The speed, resolution, bandwidth, and single-supply operation are suited for applications in radar, imaging, high-speed acquisition, and communications. A multistage pipelined architecture with output error correction logic provides for no missing codes over the full operating temperature range. Internal control registers are used to program the ADC into the desired mode. The THS1007 consists of four analog inputs, which are sampled simultaneously. These inputs can be selected individually and configured to single-ended or differential inputs. Internal reference voltages for the ADC (1.5 V and 3.5 V) are provided. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. The THS1007C is characterized for operation from 0°C to 70°C, and the THS1007I is characterized for operation from ...
发表于 04-18 19:06 •
108次
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信息描述The THS10064 is a CMOS, low-power, 10-bit, 6 MSPS analog-to-digital converter (ADC). The speed, resolution, bandwidth, and single-supply operation are suited for applications in radar, imaging, high-speed acquisition, and communications. A multistage pipelined architecture with output error correction logic provides for no missing codes over the full operating temperature range. Internal control registers are used to program the ADC into the desired mode. The THS10064 consists of four analog inputs, which are sampled simultaneously. These inputs can be selected individually and configured to single-ended or differential inputs. An integrated 16 word deep FIFO allows the storage of data in order to improve data transfers to the processor. Internal reference voltages for the ADC (1.5 V and 3.5 V) are provided. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. Two diffe...
发表于 04-18 19:06 •
147次
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