您好,欢迎来电子发烧友网! ,新用户?[免费注册]

您的位置:电子发烧友网 > 源码下载 > VHDL/Verilog/EDA源码 >

汉字点阵显示与数字抢答器的VHDL程序设计(源代码分享)

大小:0.1 MB 人气: 2017-12-02 需要积分:0

  汉字点阵显示VHDL源程序

  library ieee;

  use ieee.std_logic_1164.all;

  use ieee.std_logic_unsigned.all;

  use ieee.std_logic_arith.all;

  enTIty hzxs is

  port(clk1,clk2:in std_logic;

  rd:out std_logic;

  we: out std_logic;

  ledw:out std_logic_vector(2 downto 0);

  d:out std_logic_vector(0 downto 7));

  end hzxs;

  architecture hav of hzxs is

  signal count:std_logic_vector(0 to 2);

  signal a: std_logic_vector(3 downto 0);

  begin

  process(clk2)

  begin

  if clk2‘event and clk2=’1‘ then

  count《=count+1;

  end if;

  ledw《=count;

  a(2 downto 0)《=count;

  end process;

  process(clk1)

  begin

  if clk1’event and clk1=‘1’ then

  a(3)《=not a(3);

  end if;

  end process;

  process(a)

  begin

  case a is

  when“0000”=》d《=“10110100”;--数

  when“0001”=》d《=“11111111”;

  when“0010”=》d《=“01001010”;

  when“0011”=》d《=“11011010”;

  when“0100”=》d《=“11110110”;

  when“0101”=》d《=“11100110”;

  when“0110”=》d《=“01110110”;

  when“0111”=》d《=“11011011”;

  when“1000”=》d《=“00010000”;--字

  when“1001”=》d《=“11111111”;

  when“1010”=》d《=“11111101”;

  when“1011”=》d《=“00001100”;

  when“1100”=》d《=“11111111”;

  when“1101”=》d《=“00010000”;

  when“1110”=》d《=“00010000”;

  when“1111”=》d《=“00001100”;

  when others=》d《=“00000000”;

  end case;

  end process;

  rd《=‘1’;

  we《=‘0’;

  end hav;

非常好我支持^.^

(0) 0%

不好我反对

(0) 0%

      发表评论

      用户评论
      评价:好评中评差评

      发表评论,获取积分! 请遵守相关规定!